High-performance ultra-low-voltage digital and RF circuits based on adaptive forward back biasing in 28nm FDSOI CMOS

The deployment of the Internet-of-Things ubiquitous sensing paradigm is constrained by the development of the four functions usually embedded in a wireless sensor node: • Power management, targeting efficient energy harvesting from the envi- ronment, conversion and storage. • Sensing, with an emphasis on versatility, energy efficiency and accuracy depending on the targeted application. • Data processing, such as feature extraction or compression, to limit the amount of data to communicate wirelessly. • RF communication, to transmit sensed and processed data to the cloud with high data-rate and low energy per bit. In this work, we explore the design of high-performance ultra-low-voltage (ULV) circuits for both the data processing and the RF communication function with a common objective: the improvement of the energy/performance trade-off. To improve this tradeoff, we rely on innovative digital and analog/RF circuits and systems design as well as on the exploitation of 28nm FDSOI CMOS process. In the last few years, FDSOI technology has emerged as an industrially-proven solution to overcome the limitations of bulk technologies and continue the trend of Moore’s law. In addition to a lower cost compared to FinFet solutions, FDSOI can provide both high-speed or low-leakage solution and is thus an interesting candidate for the implementation of highly-efficient ultra-low-power circuits. Its performances rely on a better electrostatic control of the channel, lower variability, lower parasitic capacitances, lower leakage, steeper subthreshold slope and wide back-biasing range compared to the body-bias range in bulk technology. Among these characteristics, the capability to apply an overdrive back bias voltage above the supply voltage is a key feature of this dissertation. We intend to look at the usefulness of forward back biasing in the design of high performance circuits related to the data processing and RF functionalities of a typical wireless sensor node by looking at three questions: How does FDSOI with its back biasing capability influence the energy/speed tradeoff in ULV digital circuits? How does FDSOI with its back biasing capability influence the power/per- formances in analog/RF circuits? How can the back biasing capability be used to design ULV radios while meeting the specifications of communication standard? As a first step, we study of the impact of back biasing on ultra-low-voltage logic by looking at the evolution of the minimum energy point for several innovative back biasing schemes from gate level to IP level. We show that overdrive forward back biasing helps to extend the design space to higher frequency of operation while keeping minimum energy. Asymmetric adaptive back biasing is presented as a way to mitigate the effect of systematic NMOS/PMOS mismatch on minimum energy point and robustness. At IP level, we prove that mixing two or three overdrive back biasing voltages can be used to reduce the energy per cycle of microcontroller cores over a wide range of frequency of operation. As a second step, we study the performances of 28nm FDSOI with its back biasing capability for analog/RF circuits. A reduction of the supply voltage of RF analog circuits, to ensure compatibility with digital parts or to improve the power consumption, strongly challenges the analog/RF design in nanometer CMOS technologies due to the limited voltage headroom. We show that reducing the supply voltage pushes devices from strong inversion to moderate inversion. Forward back biasing can be used to mitigate this trend and increase the design space. We further show the impact of technology scaling on important RF figure of merits to highlight the ability of 28nm FDSOI to trade speed for power. Then, we illustrate this ability at circuit level with one objective: optimizing a wideband low noise amplifier for the hot topic of software-defined radios. We analyze a wideband LNA to show that technology scaling and forward back biasing shift the minimum supply voltage limitation from the bandwidth constraint to the noise constraint. Finally, we demonstrate the potential of back-biasing in 28nm FDSOI to push digital RF circuits in the ULV domain with a silicon demonstrator: SleepTalker. This chip is an IEEE 802.15.4a ultra-wideband transmitter SoC designed for ultra-low-voltage in 28nm FDSOI CMOS. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit with embedded power management, highly duty-cycled digital baseband and programmable pulse shaping for compliance with regulation. A wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction allowing 3.5 to 4.5GHz operation at 0.55V thereby showing that back-biasing can act as an enabler for ultra-low-voltage RF circuits. The forward back biasing is also used for PVT compensation and tuning of both the carrier frequency and the output power which shows how it can be used as a control knob for RF functionality.(FSA - Sciences de l'ingénieur) -- UCL, 201

Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range

A 65nm 1V to 0.5V Linear Regulator with Ultra Low Quiescent Current for Mixed-Signal ULV SoCs

A linear regulator for point of load power delivery with 280nA quiescent current and 0:008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0:5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0:5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process

Scaling Perspectives of ULV Microcontroller Cores to 28nm UTBB FDSOI CMOS

Short-channel effects and variability in bulk technolo-gies limit the interest of CMOS technology scaling for ultra-low-voltage (ULV) logic below 65nm because of the resulting penalty in the energy efficiency. FDSOI has already been predicted to be a good candidate to keep an excellent energy efficiency while increasing speed at ULV. In this paper, we confirm this result by synthesis re-sults of microcontrollers at 0.35V. We show that the use of a mix of overdrive forward back biasing (FBB) voltages in 28nm FDSOI fur-ther improves the energy efficiency. Compare to bulk 65nm CMOS, we were able to reduce the energy per cycle by 64% or increase the frequency of operation by 7x while maintaining energy per operation below 3 W/MHz over a wide frequency range

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs

Adding vision capabilities to wireless sensors nodes (WSN) for the Internet-of-Things requires imagers working at ultra-low power (ULP) in nanometer CMOS systems-on-chip (SoCs). Such performance can be obtained with time-based digital pixel sensors (DPS) working at ultra-low voltage (ULV), at the expense of lower dynamic range, higher fixed-pattern noise (FPN) and thus poorer image quality. To address this problem, three key techniques were developed in this work for DPS pixels: wide-range adaptive body biasing, low-Ron gating of the 2-transistor in-pixel comparator and digital readout performing delta-reset sampling with low switching activity and robust timing closure. These concepts were demonstrated by designing and fabricating a 128$times$128 CMOS image sensor array in a 65 nm low-power CMOS logic process. Operating at 0.5 V, it features an FPN of 0.66%, a dynamic range of 42 dB and a fill factor of 57% with a 4 µm pixel pitch, while consuming only 17 pJ/(frame.pixel) and 8.8 µW at 32 fps. These performances combined with the small silicon area of 0.69 mm 2 makes the imager perfectly suitable for integration in ULP SoCs, targeting WSN applications

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping

Achieving wireless communications at 5–30 Mb/s in energy-harvesting Internet-of-Things (IoT) applications requires energy efficiencies better than 100 pJ/b. Impulse-radio ultra-wideband (UWB) communications offer an efficient way to achieve high data rate at ultra-low power for short-range links. We propose a digital UWB transmitter (TX) system-on-chip (SoC) designed for ultra-low voltage in 28-nm FDSOI CMOS. It features a PLL-free architecture, which exploits the duty-cycling nature of impulse radio through aggressive duty cycling within the pulse modulation time slot for high energy efficiency and minimum jitter accumulation. Wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. To ensure spectral compliance with output power regulations without the use of bulky and expensive off-chip filters, a programmable pulse-shaping functionality is integrated in the digital power amplifier based on a 7–9-GS/s, 5-b current DAC. Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the TX alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2

Multi-VT ultra-low-power FPGA implementation in 65nm CMOS technology

The development of sustainable and durable ultra- low-power SoC calls for flexibility integration in the design flow. Reconfigurable logic circumvents the intrinsic low speed performances of software processing in microcontrollers but FPGA fabrics to be embedded suffer from a high power overhead compared to dedicated ASICs. We show that, by combining a power-oriented implementation using multi-VT , a careful repar- tition of different MOS flavors, and an aggressive scaling of core voltage, the dynamic power consumption can be reduced below 6μW/tile at 50MHz switching target and the leakage power consumption can be brought down below 0.5μW/tile. Simulation results show that a 16-bits multiplier, mapped onto the fabric developed with these techniques, is characterized by an energy per cycle as low as 2.5pJ

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test

Improving Noise and Linearity of CMOS Wideband Inductorless Balun LNAs for 10-GHz Software-Defined Radios in 28nm FDSOI

This paper presents the analysis and optimization of inductorless balun low-noise amplifiers (LNA) in a 28-nm fully-depleted SOI CMOS technology for wideband universal software-defined radio transceivers by means of an algorithm that optimizes the main figures of merit. An optimum combination of two techniques is provided leading to a new topology that overcomes the main tradeoffs of the previous circuits improving both linearity and noise with competitive bandwidth (BW), gain and power. Post-layout simulations show a BW of 10 GHz, a gain of 17 dB, an IIP3 of 7.4 dBm, and a NF of 3.4 dB with only 2.5 mW power consumption from a 1-V supply