Efficient Parameters Selection for CNTFET Modelling Using Artificial Neural Networks

Abstract In this article different types of artificial neural networks (ANN) were used for CNTFET (carbon nanotube transistors) simulation. CNTFET is one of the most likely alternatives to silicon transistors due to its excellent electronic properties. In determining the accurate output drain current of CNTFET, time lapsed and accuracy of different simulation methods were compared. The training data for ANNs were obtained by numerical ballistic FETToy model which is not directly applicable in circuit simulators like HSPICE. The ANN models were simulated in MATLAB R2010a software. In order to achieve more effective and consistent features, the UTA method was used and the overall performance of the models was tested in MATLAB. Finally the fast and accurate structure was introduced as a sub circuit for implementation in HSPICE simulator and then the implemented model was used to simulate a current source and an inverter circuit. Results indicate that the proposed ANN model is suitable for nanoscale circuits to be used in simulators like HSPICE

Introduction of the structure, modeling and analysis of junctionless heterostructure Si/Si1-xGex transistor

In Junctionless transistors, the source-channel-drain doping is of the same type and level, hence, the process of making Junctionless transistors is easier than inverting mode transistor. Despite this benefit, reducing the transconductance of Junctionless transistors due to reduced carrier velocity makes the operation of this type of transistor difficult for analog, radio frequency and high frequency noise usages. An effective method that increases the trans-conductance of Junctionless transistors without reducing efficiency is using a heterogeneous structure in the channel. In the present article, using Si and Si1-xGex materials in the channel is proposed and modeled so as to enhance the transconductance of Junctionless transistor. The special structure of the proposed transistor, called JL-Si / Si1-xGex, eliminates the intervalley scattering between valleys of ∆2 and ∆4. This increases the velocity of the electron and consequently enhances the transconductance. The outcomes of the modelling of the proposed JL-Si / Si1-xGex heterostructure transistor indicate the maximum transconductance of 2.5 mS / um, which increases 50% compared to similar silicon transistor. Moreover, calculations which are extracted from modelling demonstrate that the proposed JL-Si / Si1-xGex transistor has a unity gain cutoff frequency of 750 GHz, minimum noise figure of 65.0 dB, and an available gain of 28.5 dB. The parameters of cut-off frequency, minimum noise figure and available gain of the proposed JL-Si / Si1-xGex transistor have been improved by 34%, 62.5% and 53%, respectively, compared to the JL-Si transistor with similar dimensions. The proposed device can be suitable candidate for RFIC applications