Simultaneous computation of model order and parameter estimation of a heating system based on particle swarm optimization for autoregressive with exogenous model

System identification is a method used to obtain a mathematical model of a system by performing analysis of input-output behavior of the system. In system identification, the procedure can be separated into four main parts. The first part is constructing an experiment to collect the input-output data of the system. Then, based on some criteria, the model order and structure are selected. The next part is to estimate the parameters of the model. For the final part, the mathematical model is verified. In this study, a new approach called simultaneous model order and parameter estimation (SMOPE), which is based on Particle Swarm Optimization (PSO), is proposed to combine model order selection and parameter estimation in one platform. In this approach, both the model order and the parameters of the system are searched simultaneously by a particle. Similar to other PSO implementation, a number of particles are utilized in the search process. In order to realize the simultaneous search of the best model order and the associated parameters, a suitable particle representation is employed. Based on a heating system case study, it is proven that the proposed approach is superior compared to some other methods in literature

Parallel Huffman decoder with an optimized look up table option on FPGA

Compression is very important for systems with limited channel bandwidth and/or limited storage size. One of the main components in image/video compression is variable length coding (VLC). This paper discusses one of the most popular VLC technique known as Huffman coding. A real time hardware parallel Huffman decoder has been successfully designed and implemented using 50,000 gate FPGA (FLEX10K20 from Altera). The parallelism is exploited in the design to achieve the high frame rate such as in JPEG and MPEG implementation. Using a parallel technique, a codeword is guaranteed to be processed within a single clock cycle. The codeword to be processed is matched with the one stored in a look up table (LUT). A LUT is needed during the coding and decoding process. In order to save memory cost, an optimized LUT is suggested. This paper does not intend to complete an optimized operating speed design, but instead only concentrates on producing a workable real-time decoder desig

Coarse Resolution Defect Localization Algorithm For An Automated Visual Pcb Inspection

One of the backbones in electronic manufacturing industry is the printed circuit board (PCB) manufacturing. Current practice in PCB manufacturing requires an etching process. This process is an irreversible process. Printing process, which is done before the etching process, caused most of the destructive defects found on the PCB. Once the laminate is etched, the defects, if exist would cause the PCB laminate to become useless. Due to the fatigue and speed requirement, manual inspection is ineffective to inspect every printed laminate. Therefore, manufacturers require an automated system to detect the defects online which may occur during the printing process. The defect is detected by utilizing wavelet-based image difference algorithm. Hence, this paper proposes an algorithm for an automated visual PCB inspection that is able to automatically locate and extract any defect on a PCB laminate. The algorithm works on the coarse resolution differenced image in order to locate the defective area on the fine resolution tested PCB image

Performance Evaluation Of Wavelet-Based Algorithm For Printed Circuit Board (PCB) Inspection

Image difference operation is frequently used in automated printed circuit board (PCB) inspection system as well as in many other image processing applications. The inspection system performance depends critically on the speed of this operation, which is a common problem related to the image difference. The goal of our technique is to achieve real time inspection using wavelet transform. This paper presents a new wavelet-based algorithm for image difference, which computes image difference to the output of the wavelet transform. The results of applying the technique to PCB images showed significant improvement on the traditional image differencing

Modeling of a ladder logic processor for high performance programmable logic controller

Today, programmable logic controllers (PLCs) is the dominant technology deployed in control automation systems in modern factories. The main modeling method of the PLC is based on ladder logic diagrams (LLDs). However, as a system gets more complex, LLD implementations poses a stumbling block in the design of more complex and real-time PLCs. Consequently, in this paper, a novel architecture for a high performance LLD implementation, which we call the Ladder Logic Processor, is proposed. In the proposed architecture, each computation of the underlying ladder logic is performed at a fixed number of clock cycles per ladder rung, regardless of the number of steps involved. Notwithstanding, the technique maintains the existing LLD paradigm where every rung is processed sequentially. The LLDs are targeted for implementation in Field Programmable Gate Arrays (FPGAs). Experimental work performed to evaluate the performance of the proposed architecture shows promising results