Optimizing silicon avalanche photodiode fabricated by standard CMOS process for 8 GHz operation

Silicon avalanche photodiode (APD) was fabricated by standard 0.18 μm CMOS process. The current-voltage characteristic and frequency response was measured for the APD with and without guard ring. With the guard ring around the perimeter of the diode junction, it shows a better performance for the maximum bandwidth but in contrast lower in responsivity. To enhance the bandwidth, the detection area and the PAD size for RF probing are optimized to 10 × 10 μm2 and 30 × 30 μm2, respectively, to decrease the device capacitance, the spacing of interdigital electrode is narrowed to 0.84 μm to decrease carrier transit time, and by cancelling the carriers photo-generated in the deep layer and the substrate because the carriers are slow diffusion carriers. As a result, the maximum bandwidth of 8 GHz was achieved along with a gain-bandwidth product of 280 GHz. © 2015 IEEE

Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)

Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET)incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was scaled to get an optimized structure. An analysis of current-voltage (I-V) of 50 nm channel length (Lg) has been done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V and increase when VDS = 1.0 V. Consequently, the threshold voltage (VT) is increased accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better for MOSFET with DP as compared to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product