426 research outputs found
Formation of Strain-Induced Quantum Dots in Gated Semiconductor Nanostructures
Elastic strain changes the energies of the conduction band in a
semiconductor, which will affect transport through a semiconductor
nanostructure. We show that the typical strains in a semiconductor
nanostructure from metal gates are large enough to create strain-induced
quantum dots (QDs). We simulate a commonly used QD device architecture, metal
gates on bulk silicon, and show the formation of strain-induced QDs. The
strain-induced QD can be eliminated by replacing the metal gates with
poly-silicon gates. Thus strain can be as important as electrostatics to QD
device operation operation.Comment: 5 pages, 3 figures, plus supplementary informatio
Simulating Capacitances to Silicon Quantum Dots: Breakdown of the Parallel Plate Capacitor Model
Many electrical applications of quantum dots rely on capacitively coupled
gates; therefore, to make reliable devices we need those gate capacitances to
be predictable and reproducible. We demonstrate in silicon nanowire quantum
dots that gate capacitances are reproducible to within 10% for nominally
identical devices. We demonstrate the experimentally that gate capacitances
scale with device dimensions. We also demonstrate that a capacitance simulator
can be used to predict measured gate capacitances to within 20%. A simple
parallel plate capacitor model can be used to predict how the capacitances
change with device dimensions; however, the parallel plate capacitor model
fails for the smallest devices because the capacitances are dominated by
fringing fields. We show how the capacitances due to fringing fields can be
quickly estimated.Comment: 4 pages, 3 figures, to be published in IEEE Trans. Nan
Fabrication and Electrical Characterization of Fully CMOS Si Single Electron Devices
We present electrical data of silicon single electron devices fabricated with
CMOS techniques and protocols. The easily tuned devices show clean Coulomb
diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In
addition, the devices exhibit robust transistor characteristics including
uniformity within about 0.5 V in the threshold voltage, gate resistances
greater than 10 G{\Omega}, and immunity to dielectric breakdown in electric
fields as high as 4 MV/cm. These results highlight the benefits in device
performance of a fully CMOS process for single electron device fabrication.Comment: 7 pages, 7 figure
Determining the Location and Cause of Unintentional Quantum Dots in a Nanowire
We determine the locations of unintentional quantum dots (U-QDs) in a silicon
nanowire with a precision of a few nanometers by comparing the capacitances to
multiple gates with a capacitance simulation. Because we observe U-QDs in the
same location of the wire in multiple devices, their cause is likely to be an
unintended consequence of the fabrication, not random atomic-scale defects as
is typically assumed. The locations of the U-QDs appear consistent with
conduction band modulation from strain from the oxide and the gates. This
allows us to suggest methods to reduce the frequency of U-QDs
Charge Offset Stability in Si Single Electron Devices with Al Gates
We report on the charge offset drift (time stability) in Si single electron
devices (SEDs) defined with aluminum (Al) gates. The size of the charge offset
drift (0.15 ) is intermediate between that of Al/AlO/Al tunnel junctions
(greater than 1 ) and Si SEDs defined with Si gates (0.01 ). This range
of values suggests that defects in the AlO are the main cause of the charge
offset drift instability
- …