Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding

Novel Electrostatic Discharge (Esd) Clamp Circuit With Low Leakage Current

A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under the ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the ESD clamp, and comparing with the conventional designs, the simulation results suggest that the proposed circuit has a lower power consumption and smaller footprint while achieving better performance

Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness

Novel Voltage Triggered Electrostatic Discharge (Esd) Detection Circuit

A novel 2×VDD-tolerant electrostatic discharge (ESD) detection circuit which uses only low-voltage devices is proposed in a 0.18 um CMOS process. Under normal operating conditions, all the devices are free from over-stress voltage threat. Our proposed detection circuit achieves a high triggering efficiency with a much smaller footprint. Comparing with the RC based detection circuit, our proposed circuit is a voltage triggered detection circuit which is immune to false triggering under the fast power-up events. SPICE simulation is carried out to evaluate the detection circuit, and the simulation results suggest that the proposed circuit could be used as a reliable 2×VDD-tolerant I/O buffer