Topological phase transition from nodal to nodeless d-wave superconductivity in electron-doped cuprate superconductors

Unlike the hole-doped cuprates, both nodal and nodeless superconductivity (SC) are observed in the electron-doped cuprates. To understand these two types of SC states, we propose a unified theory by considering the two-dimensional t-J model in proximity to an antiferromagnetic (AF) long-range ordering state. Within the slave-boson mean-field approximation, the d-wave pairing symmetry is still the most energetically favorable even in the presence of the external AF field. In the nodal phase, it is found that the nodes carry vorticity and are protected by the adjoint symmetry of time-reversal and one unit lattice translation. Robust edge modes are obtained, suggesting the nodal d-wave SC being a topological weak-pairing phase. As decreasing the doping concentration or increasing the AF field, the nodes with opposite vorticity annihilate and the nodeless strong-pairing phase emerges. The topological phase transition is characterized by a critical point with anisotropic Bogoliubov quasiparticles, and a universal understanding is thus established for all electron-doped cuprates.Comment: 7 pages, 5 figures; published versio

Two-dimensional topological superconducting phases emerged from d-wave superconductors in proximity to antiferromagnets

Motivated by the recent observations of nodeless superconductivity in the monolayer CuO$_{2}$ grown on the Bi$_{2}$Sr$_{2}$CaCu$_{2}$O$_{8+\delta }$ substrates, we study the two-dimensional superconducting (SC) phases described by the two-dimensional $t$-$J$ model in proximity to an antiferromagnetic (AF) insulator. We found that (i) the nodal d-wave SC state can be driven via a continuous transition into a nodeless d-wave pairing state by the proximity induced AF field. (ii) The energetically favorable pairing states in the strong field regime have extended s-wave symmetry and can be nodal or nodeless. (iii) Between the pure d-wave and s-wave paired phases, there emerge two topologically distinct SC phases with ($s+$i$d$) symmetry, i.e., the weak and strong pairing phases, and the weak pairing phase is found to be a $Z_{2}$ topological superconductor protected by valley symmetry, exhibiting robust gapless non-chiral edge modes. These findings strongly suggest that the high-$T_{c}$ superconductors in proximity to antiferromagnets can realize fully gapped symmetry protected topological SC.Comment: 7 pages, 4 figures; revised versio

Design of a High-Speed Architecture for Stabilization of Video Captured Under Non-Uniform Lighting Conditions

Video captured in shaky conditions may lead to vibrations. A robust algorithm to immobilize the video by compensating for the vibrations from physical settings of the camera is presented in this dissertation. A very high performance hardware architecture on Field Programmable Gate Array (FPGA) technology is also developed for the implementation of the stabilization system. Stabilization of video sequences captured under non-uniform lighting conditions begins with a nonlinear enhancement process. This improves the visibility of the scene captured from physical sensing devices which have limited dynamic range. This physical limitation causes the saturated region of the image to shadow out the rest of the scene. It is therefore desirable to bring back a more uniform scene which eliminates the shadows to a certain extent. Stabilization of video requires the estimation of global motion parameters. By obtaining reliable background motion, the video can be spatially transformed to the reference sequence thereby eliminating the unintended motion of the camera. A reflectance-illuminance model for video enhancement is used in this research work to improve the visibility and quality of the scene. With fast color space conversion, the computational complexity is reduced to a minimum. The basic video stabilization model is formulated and configured for hardware implementation. Such a model involves evaluation of reliable features for tracking, motion estimation, and affine transformation to map the display coordinates of a stabilized sequence. The multiplications, divisions and exponentiations are replaced by simple arithmetic and logic operations using improved log-domain computations in the hardware modules. On Xilinx\u27s Virtex II 2V8000-5 FPGA platform, the prototype system consumes 59% logic slices, 30% flip-flops, 34% lookup tables, 35% embedded RAMs and two ZBT frame buffers. The system is capable of rendering 180.9 million pixels per second (mpps) and consumes approximately 30.6 watts of power at 1.5 volts. With a 1024×1024 frame, the throughput is equivalent to 172 frames per second (fps). Future work will optimize the performance-resource trade-off to meet the specific needs of the applications. It further extends the model for extraction and tracking of moving objects as our model inherently encapsulates the attributes of spatial distortion and motion prediction to reduce complexity. With these parameters to narrow down the processing range, it is possible to achieve a minimum of 20 fps on desktop computers with Intel Core 2 Duo or Quad Core CPUs and 2GB DDR2 memory without a dedicated hardware

A Multiplier-Less Architecture for High Speed Computation of Multi-Dimensional Convolution

One of the most computationally intensive operations in digital image/video processing systems is multi-dimensional convolution. Every image/video processor needs the convolution module in its pre-processing stage. Fast and efficient design of the convolution module in an application specific system is a great challenge in VLSI (Very Large Scale Integration) design. Convolution operator requires a large set of multipliers and accumulators. A high precision multiplier takes enormous amount of VLSI area and it consumes more power. Hence reduction of the number of multipliers is another important challenge in VLSI design. A multiplier-less architecture for the design of a multi-dimensional convolution module is proposed in this thesis. The convolution expression is suitably partitioned to make it appropriate for overall pipelining and internal parallelism in the architecture design. An absolute flexibility is provided in the architecture for choosing the kernel characteristics in the convolution module. A novel architecture for performing convolution with symmetric kernels is also proposed in this thesis. This quadrant symmetric architecture exploits the symmetry of the kernels and performs computation with one quarter area of the kernel. Since the kernel characteristics are the same in all other three quarters, the intermediate results are reused and manipulated accordingly to obtain the final convolution result. This design reduces the VLSI area by about 75%. A new concept of log2 and inverse-log2 computation by an approximation process is also presented in this research. This leads to the elimination of the need for multipliers in the generic architecture by employing only adders and shifters for computation. The proposed architectures are implemented in a FPGA (Field Programmable Gate Array) environment on Xilinx\u27s Virtex II 2v2000ff896-4 chip with a clock frequency of 99 MHz. It is observed that the new design reduces the VLSI area further by about 10% in addition to the reduction of power consumption. It is also observed that the new design could generate an output pixel in every clock cycle. Research work is in progress to employ the concept of log2 and inverse-log2 computations in building multiplier-less architectures for auto-correlation and cross-correlation functions