Les cathares au jour le Jour, Confessions inédites de cathares quercynois

Blaquière Henri, Dossat Yves. Les cathares au jour le Jour, Confessions inédites de cathares quercynois. In: Cathares en Languedoc. Toulouse : Éditions Privat, 1968. pp. 259-298. (Cahiers de Fanjeaux, 3

A New Accurate and Hierarchical Timing Analysis Approach

A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with circuit level accuracy. The efficiency is obtained by rapidly identifying the critical portions of the circuit at high hierarchical levels with rough delay models. These portions are then successively studied at more detailed levels for maximal accuracy. This procedure, implemented and applied to several circuits, is shown to significantly reduce the analysis time. 1 Introduction For some applications, the timing performance estimation time of a circuit is more important than the accuracy. For others, the accuracy cannot be sacrificed and there is a need for efficient and accurate timing analysis. This need increases with the complexity and speed of VLSI systems. Speed-up is usually achieved by sacrificing delay accuracy using abstract delay models, such as switch (e.g. [1, 2]) or block (e.g. [3]) level instead of circuit level (e.g. [4]). However, constraining timing analysis tools to l..