QoS support in embedded networks and NoC

Quality of service (QoS) requirements such as priorities, packet delivery and packet delivery time are important and critical for embedded networks and networkson-chip (NoC) [1]. We consider mechanisms for QoS support in the SpaceFibre, SpaceWire and GigaSpaceWire protocols, possibility of using them in embedded networks and NoC. In the article we analyze approaches for QoS provision, their feasibility and value of QoS in SpaceWire/GigaSpaceWire and in SpaceFibre networks. Networks with different topologies and traffic pattern are used to study and to evaluate the performance. Various traffic types such as the data packets, streaming data, commands will be transmitted in networks. Data delivery characteristics for SpaceFibre and SpaceWire/GigaSpaceWire networks are analyzed and compared. Also we compare characteristics that are achievable in NoC, which are based on QoS mechanisms of SpaceFibre, SpaceWire and GigaSpaceWire. Hardware costs are one of the main constraints for embedded networks and NoC. Therefore we compare hardware costs of basic SpaceFibre, SpaceWire and GigaSpaceWire routers

The network calculator for NoC buffer space evaluation

In this paper we discuss the problem of choosing the buffer size in the Network-on-Chip routers. This problem is closely related to other problems that arise in NoC's design - choosing of interconnection structure between nodes and data paths in the system. It is a complex multicriteria problem. The design space exploration approach is widely used to solve such problems. In this approach each possible system configuration corresponds to a point in the Design Space. For each point, the user evaluates whether it satisfies its requirements and determine the future direction of motion in Design Space. The network calculators are used to calculate values of the NoC's parameters at each point. We consider the existing methods of buffer sizes calculation, their capabilities and limitations. We suggest the method of buffer space calculation for NoC with arbitrary topology and the algorithm of the corresponding network calculator

Second revision of the STP-ISS transport protocol for on-board spacewire networks

The paper provides an overview of the second revision of the Transport protocol STP-ISS, which is developed for SpaceWire on-board networks. Current R&D activity is performed by the specialists of SUAI and JSC “ISS”. The paper shortly compares two revisions of the specification and describes the main mechanisms and quality of service types of the second revision of the protocol. STP-ISS is planned to be used for the next generation spacecrafts

Reconfigurable NoC development with fault mitigation

An ability of faults mitigation becomes one of the main requirements for network-on-chip (NoC) embedded systems that are manufactured with thin design rules. Other requirements are for area, power consumption and QoS. Altogether these requirements lead to inconsistencies in NoC development process. In this paper we discuss approaches for resolving this conflict by the use of the dynamically reconfigurable NoC. We suggest a methodology for development of NoC with fault mitigation support The methodology allows to take into account specifics of design process and operating conditions in the implementation of a particular project. For verification of the suggested approach we use analysis and simulation. We suggest an approach to simulation that enables dynamic failure injection

Structural Redundancy and Design Space Exploration Method for the Hardware Components with Fault Mitigation Design

Fault mitigation for modern embedded systems is a necessary feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault protection that need to be implemented. Another parameter of embedded system – area. It is one of most critical parameters for SoC in embedded systems and is strongly constrained. Increasing fault protection leads to growing of the SoC’s area. In this situation, it is necessary to know how strong the fault mitigation is and how it effects on the area. We propose the method for development of hardware components that can help to evaluate project from point of area constraints and fault probability requirements

The Components Spatial Redundancy Method Based on Design Space Exploration

The fault mitigation for modern embedded systems developed by thin design rules (40 nm and less) is necessary feature due to accelerating aging and manufacturing defects, for which diagnosis during the chip testing at fabric is impossible. Different ways of spatial redundancy are used for fault mitigation in the SoC. They provide different achievable mean time between failures (MTBF). For various embedded systems a different lifetime is planned, therefore fault probability is required. Realization of these methods has different hardware cost (additional area on the chip). The area is one of most critical parameters for SoC in embedded systems and is strongly constrained. We propose the method for development of components’ spatial redundancy. Method is based on design space exploration (DSE). It allows to select design spatial redundancy with considering area constraints and fault probability requirements

Fast Static Performance Analysis of Parallel Program Schemes

During the embedded system development an estimation of software performance on different hardware is needed. Estimation of the expected acceleration of program execution on various numbers of processors, estimation of computation space etc. Such estimations, as other aspects of performance analysis complex, should help with different problems that arise at the intersection of software and hardware parts. For example, selection of the most successful hardware platform from available options for current program solution or modernization of the program for better resource use of given hardware platform and achieve best performance. In the paper tool of static analysis is considered. It is a part of the complex of program performance analysis in integrated development environment VIPE for perspective multicore embedded systems

STP-ISS Transport Protocol Overview and Modeling

The paper is concerned with the development of the Transport protocol “STP-ISS” for SpaceWire networks. Firstly we give a brief overview of transport protocols which are intended to operate over SpaceWire: RMAP, CCSDS PTP, STUP, JRDDP and STP. Hereinafter, the paper presents the first revision of the new STP-ISS transport protocol which was developed in accordance with the results of the overview and technical requirements to the transport protocol. Finally, we describe STP-ISS modeling, which was very efficient for the STP-ISS protocol development, testing, analysis and improvement. This paper describes three modeling directions: C++ reference code, SDL-specification and SystemC network model