Binarized neural network of diode array with high concordance to vector–matrix multiplication

Abstract In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector–matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN

Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

Abstract In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems

Reconfigurable Logic‐In‐Memory Cell Comprising Triple‐Gated Feedback Field‐Effect Transistors

Abstract A reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as reconfigurable logic gates. The R‐LIM cell is constructed with triple‐gated (TG) feedback field‐effect transistors (FBFETs) that are reconfigured in n‐channel or p‐channel modes via electrostatic doping. Each TG FBFET has one control gate electrode and two program‐gate electrodes that determine the channel mode. Their reconfigurability enables the symmetrical operation of the n‐channel and p‐channel modes through an on‐current ratio of 1:04. Furthermore, the R‐LIM cell performs eight Boolean logic operations, storing the logic outputs for ≈100 s under zero‐bias conditions. The R‐LIM cell is useful for developing in‐memory computing systems with high energy efficiency and functional logic

Bidirectional Synaptic Operations of Triple‐Gated Silicon Nanosheet Transistors with Reconfigurable Memory Characteristics

Abstract In this study, a triple‐gated transistor with a p+‐i‐n+ silicon nanosheet (NS) is proposed as a single synaptic device, and bidirectional synaptic functions are realized using reconfigurable memory characteristics. The triple‐gated NS transistor features steep switching and bistable characteristics with a subthreshold swing below 5 mV dec−1 and an ON/OFF current ratio of ≈5 × 106 for both the n‐ and p‐channel modes. This transistor exhibits electrically symmetric reconfigurable memory characteristics with an ON current ratio of 1.02 for the n‐ and p‐channel modes. Moreover, the bidirectional synaptic weight updates of binarized spike‐timing‐dependent plasticity learning are successfully performed in a single transistor. This study demonstrates the potential of a triple‐gated NS transistor for achieving compact synaptic arrays in large‐scale silicon‐based neuromorphic computing systems