A Dual-mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times

One of the obstacles to using RISC processors in a hard real-time environment is the unpredictability of caches. This unpredictability stems from basing them on a design that tries to optimize the average case execution time. In this paper, we propose a dual mode instruction prefetch scheme as an alternative to instruction caching schemes. In the proposed scheme, a thread is associated with each instruction block. The thread indicates the instruction block that is to be prefetched once the block containing it is accessed by the processor. The proposed scheme operates in two different modes: real-time and non real-time modes. In the real-time mode, the prefetching of instruction blocks is made in the direction that improves the worst case execution time. For this purpose, the thread is generated by the compiler through an analysis of the worst case execution path. In the non real-time mode, the thread is dynamically updated so that it indicates the instruction block that is most likely..

Enhanced Analysis of Cache-related Preemption Delay in Fixed-priority Preemptive Scheduling

We propose an enhanced technique for analyzing and thus, bounding cache-related preemption delay in fixedpriority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache-related preemption delay. Second, the technique considers phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache-related preemption delay. This paper also compares the proposed technique with previous techniques. The results show that the proposed technique gives up to 60% tighter prediction of the worst case response time than the previous techniques. 1. Introduction In a real-time computing system, tasks have timing constraints in..

Reduced expression of alanyl aminopeptidase is a robust biomarker of non‐familial adenomatous polyposis and non‐hereditary nonpolyposis colorectal cancer syndrome early‐onset colorectal cancer

Abstract Background Early‐onset colorectal cancer (EOCRC) has been increasing in incidence worldwide but its genomic pathogenesis is mostly undetermined. This study aimed to identify robust EOCRC‐specific gene expression patterns in non‐familial adenomatous polyposis (FAP) and non‐hereditary nonpolyposis colorectal cancer syndrome (HNPCC) EOCRC. Method We first performed gene expression profiling analysis using RNA sequencing of discovery cohort comprised of 49 EOCRC (age 70) specimens. To obtain robust gene expression data from this analysis, we validated differentially expressed genes (DEGs) through TCGA cohort (EOCRC:59 samples, LOCRC:229 samples) and our validation cohort (EOCRC:72 samples, LOCRC:43 samples) using real‐time RT‐PCR. After the validation of DEGs, we validated the selected gene at protein levels using Western blotting. To identify whether genomic methylation regulates the expression of a particular gene, we selected methylation sites using The Cancer Genome Atlas (TCGA) datasets and validated them by pyrosequencing in our validation cohort. Results The EOCRC patients included in this study had significantly more prominent family history of cancer than the LOCRC patients (23 [46.9%] vs. 13 [26%], p = 0.050). Alanyl aminopeptidase (ANPEP) was significantly downregulated in the EOCRC tissues (FC = 1.78, p = 0.0007) and was also commonly downregulated in the TCGA cohort (FC = −1.08, p = 0.0021). Moreover, the ANPEP mRNA and protein expression levels were significantly downregulated in the EOCRC tissues of our validation cohort (p = 0.037 and 0.027). In comparisons of the normal and tumor tissues in public datasets, the ANPEP level was significantly lower in the tumor tissue in the TCGA dataset (p < 2.2 × 10−16) and GSE196006 dataset (p = 0.0005). Furthermore, the ANPEP expression level did not show a decreasing tendency at a young age in the normal colon tissue of the GTEx dataset. Lastly, the hypermethylation of cg26222247 in ANPEP was identified to be weakly associated with reduced ANPEP expression in our EOCRC cohort. Conclusion The reduced expression of ANPEP was identified as a novel biomarker of non‐FAP and non‐HNPCC EOCRC

An Accurate Instruction Cache Analysis Technique for Real-time Systems

An accurate and reliable estimation of a task&apos;s worst case execution time (WCET) is crucial for scheduling of real-time tasks. However, instruction caches, which are extensively used in computer systems today, impose a serious problem in analyzing the WCETs of tasks. The problem stems from the fact that the cache hit or miss of an instruction reference can be known only after the worst case execution path has been found and the worst case execution path, on the other hand, can be located only after the cache hit or miss of every instruction reference is known. This cyclic dependency, in many cases, leads to a pessimistic estimation of WCETs. This paper proposes an analysis technique that is immune from the above cyclic dependency and accurately predicts the WCETs of tasks in the presence of instruction caches. The key to the proposed technique is an extension of the timing schema[16] so that the timing variation due to instruction caches can be accurately accounted for. This paper also..

Bounding Cache-related Preemption Delay for Real-time Systems

Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap between the processor and main memory. However, its use in multitasking computer systems introduces additional preemption delay due to reloading of memory blocks that were replaced during preemption. This cache-related preemption delay poses a serious problem in real-time computing systems where predictability is of utmost importance. In this paper, we propose an enhanced technique for analyzing and thus, bounding the cache-related preemption delay in fixed-priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache-related preemption delay. Second, the technique considers phasing of tasks to eliminate many infeasible task interactions. These tw..