Multifunctional amorphous metal oxide thin films – Structure transformation for various functions

Metal oxides are well-known high-k dielectric materials since the early solid state electronics age. However, they were rarely used in modern IC chips except as charge storage layers in MOS capacitors. Recently, due to the performance and reliability issues of the nm thick SiO2 in the gate dielectric application, metal oxide high-k dielectrics become popular alternatives. For the most advanced MOSFET, the sub nm EOT metal oxide is the preferred choice for the gate dielectric for its low leakage current and high reliability. Separately, metal oxides, such as IGZO or ZnO, are popular semiconductor materials in thin film transistors (TFTs) because of its high field effect mobility, e.g., 10 to 100 times that of the a-Si:H TFT. For above applications, the crystalline structure is preferable. For example, for the same metal oxide dielectric, the k value of the crystalline film can be several times higher than that of the amorphous film. TFTs made of the crystalline ZnO semiconductor film have much higher mobilities than those made of the amorphous ZnO semiconductor film. However, for practical applications, only amorphous films are used in products considering the repeatability, reliability, and manufacturability factors. In this paper, the author will discuss the versatility of the amorphous metal oxide high-k thin film through transformation of the structure in simple process steps. For example, the sputter deposited zirconium doped hafnium oxide (ZrHfO) high-k dielectric can be made into the sub 1 nm EOT gate dielectric on Si wafer. By inserting a very thin metal, semiconductor, or dielectric layer in the ZrHfO film during the sputtering process and subsequently annealed with a RTP step, a nanocrystal-embedded dielectric structure is formed, which is a nonvolatile memory device. Each nanocrystal can store a single electron. Even holes can be stored in this kind of device once the proper nanocrystal material is chosen. Furthermore, nano resistors can be formed in the high-k film after a dielectric breakdown step. In the low voltage operation range, the new structure performs like a diode except the current increases linearly not exponentially with the applied voltage. The nano resistor structure can emit light under the high voltage stress condition, which is called the solid state incandescent LED (SSI-LED). The light emission phenomenon can last for more than 20,000 hours in air without failure. Among many possible applications, the SSI-LED can be used to fabricate the on-chip optical interconnect. 1. Y. Kuo, invited, “Nanocrystals Embedded High-k Nonvolatile Memories – bulk film and nanocrystal material effects,” ECS Trans., 53(4), 121-128 (2013). 2. Y. Kuo, “A Solid State Thin Film Incandescent Light Emitting Device,” IEEE Trans. Elec. Dev., 62(11), 3536-3540 (2015). 3. Y. Kuo, “A new type of solid state incandescent LED (SSI-LED) prepared by sputter deposited metal oxide thin film on Si wafer,” 13th ISSP Proc., 20-24 (2015). 4. Y. Kuo, “A Metal Oxide Antifuse-Diode Device,” ECS Trans. Low-Dimensional Nanoscale Electronic and Photonic Devices 8, 69(12) 23-29 (2015

Invited; New development on plasma-based copper etch at room temperature

Copper (Cu) is the most popular interconnect material for ULSICs, large-area TFTs, and many optoelectronics. Its high conductivity is critical to signal transmission. It also has high reliability which warranties the product’s long lifetime. However, Cu cannot be etched into fine lines using the conventional plasma etching method due to the low volatility of the reaction product. There are many efforts in removing the plasma-Cu reaction product, such as exposing the surface to the high ion bombardment energy or high energy light source. They are not suitable for production requirements with regard to the etch rate, uniformity, and cost. The CMP method was introduced to the industry to solve the problem. Although it is widely used in IC production, there are many issues, such as complicated process steps, poor endpoint control, dishing, high cost, and potential environmental contamination. Please click Download on the upper right corner to see the full abstract

Nano-resistors based devices - effects of size and structure on performance

Recently, a new type of nano-resistor device that can emit the broad bad ward white light as well as show the diode-like behavior has been reported (1,2,3). They are potentially applicable to lighting, on-chip interconnects, nonvolatile memories, nano-heaters, etc. The nan-resistor device can be operated continuously for more than 20,000 hours in air without a passivation layer. The unique phenomenon of simultaneously formation of a large number of nm-sized nano-resistors from the breakdown of a MOS capacitor was never reported in the open literature until our publication. In this paper, new results on nano-resistor devices will be discussed. The device size effect on the light emission phenomenon, as shown in Fig. 1, will be explained from the distribution of nano-resistors across the gate electrode and the nano-resistor formation mechanism. In addition, the increase of the light emission efficiency from the embedding of nanocrystals in the gate dielectric layer will be discussed based on defects enhanced nano-resistors formation process. Furthermore, for the large array application, the crosstalk among adjacent devices can be avoided using the coplanar structure, which will be shown in this paper. The device performance will be compared with that of the vertical-structured device. Please click Additional Files below to see the full abstract

Reliability of plasma-etched copper lines on a glass substrate

Copper (Cu) thin films can be etched into 0.3 micrometer Cu patterns, as shown in Figure 1. This process has been used in the fabrication of large-area thin film transistor (TFT) arrays for LCDs, interconnect lines in high density BiCMOS circuits, and source, drain and gate electrodes of a-Si:H TFTs (1,2). The reliability of the Cu line is usually investigated with the isothermal electromigration (EM) method (3). In almost all studies, the Cu line was prepared on the silicon substrate coated with a dielectric layer. There are few studies on Cu line lifetime on the glass substrate. Also, the EM failure investigation was focused on the line broken time, which could be influenced by the edge roughness, step coverage, current density, etc. (4). The physical and structure changes of the Cu line during the EM stress time are often neglected (5). In this paper, authors discuss the application of the plasma etched Cu line for the SSI-LED array. It allows the driving of the individual device for light emitting at specified conditions, which enables applications in displays, optical interconnects, etc. The transformation of the Cu line from a continuous pattern to the broken state will be reviewed. The temperature change with respect to the stress current density and the lifetime will be discussed. In summary, the room temperature plasma-based Cu etch process can be applied to a wide range of electronic and optoelectronic products. The understanding of the reliability of the Cu line is important for these applications. Please click Additional Files below to see the full abstract