37 research outputs found

    Efficient Architecture of Variable Size HEVC 2D-DCT for FPGA Platforms

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    This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4×4, 8×8, 16×16, and 32×32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4K@30fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31-64% in hardware cost

    Refining Wi-Fi Based Indoor Localization with Li-Fi Assisted Model Calibration in Smart Buildings

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    In recent years, there has been an increasing number of information technologies utilized in buildings to advance the idea of "smart buildings". Among various potential techniques, the use of Wi-Fi based indoor positioning allows to locate and track smartphone users inside a building, therefore, location-aware intelligent solutions can be applied to control and of building operations. These location-aware indoor services (e.g., path finding, internet of things, location based advertising) demand real-time accurate indoor localization, which is a key issue to guarantee high quality of service in smart buildings. This paper presents a new Wi-Fi based indoor localization technique that achieves significantly improvement of indoor positioning accuracy with the help of Li-Fi assisted coefficient calibration. The proposed technique leverages indoor existing Li-Fi lighting and Wi-Fi infrastructure, and results in a cost-effective and user-convenient indoor accurate localization framework. In this work, experimental study and measurements are conducted to verify the performance of the proposed idea. The results substantiate the concept of refining Wi-Fi based indoor localization with Li-Fi assisted computation calibration.Comment: International Conference on Computing in Civil and Building Engineering (ICCCBE) 201

    Power Efficient SRAM Design with Integrated Bit Line Charge Pump

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    Bit line toggling of SRAM systems in write operations leads to the largest portion of power dissipation. To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit line charge. In this work, a power-efficient charge recycling SRAM is designed and implemented in 180nm CMOS technology. Post-layout simulation demonstrates an 11% of power saving and 3.8% of area overhead, if the bit width of SRAM is chosen as 8. Alternatively, 22% of power reduction is obtained if the bit width of SRAM is extended to 64. Compared with existing charge recycling SRAM schemes, this proposed SRAM is robust to process variation, demonstrates good read/write stability, and illustrates better trade-off between design complexity and power reduction

    A fully integrated RSSI and an ultra-low power SAR ADC for 5.8 GHz DSRC ETC transceiver

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    This study presents a monolithic received signal strength indicator (RSSI) and an ultra-low power SAR ADC for 5.8 GHz DSRC transceiver in China electronic toll collection systems. In order to meet the stringent requirement of wide input range for the transceiver, two RSSIs collaborate with auxiliary ADC circuits to provide the digitalized received signal strength to the digital baseband of a transceiver. The RSSI design achieves fast transient response and low power consumption with a small die area by using internal active low-pass filters instead of external passive ones. The proposed design has been fabricated using a 0.13 μm 2P6M CMOS technology. Measurement results show that the overall input dynamic range is 86 dB with an accuracy of ±1.72 dB and a transient response of less than 2 μs. Compared with the state-of-the-art designs in the literature, the overall input range and transient settling time are improved by at least 14.6%, and 300%, respectively

    A 5.8 GHz DSRC Digitally Controlled CMOS RF-SoC Transceiver for China ETC

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    This paper presents a 5.8 GHz dedicated short range communication (DSRC) CMOS RF-SoC transceiver with digitally controlled RF architecture for China electronic toll collection (ETC) system. The operation of key RF blocks, such as ASK modulator, power amplifier, LNA, and mixer, are directly controlled by digital baseband. Compared with state-of-the-art designs in literature, this work demonstrates remarkable advantages in design simplicity, Tx output peak power, adjacent channel power ratio (ACPR), dynamic range, occupied bandwidth (OBW), bit error rate (BER), and so on

    Efficient Algorithm Adaptations and Fully Parallel Hardware Architecture of H.265/HEVC Intra Encoder

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    Satellite Image-Based Methods of Spatiotemporal Analysis on Sustainable Urban Land Use Change and the Driving Factors: A Case Study in Caofeidian and the Suburbs, China

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    As a typical rapid-development seaport area in coastal cities, such as Caofeidian, the study on the spatiotemporal changes of urban land use and its surrounding rural areas is valuable and significant in reference to the future urban planning and land policies in similar coastal areas of China or other countries. Based on satellite images, this research processes images in different years for summarizing the changes of vegetation, urban areas, and water areas in Caofeidian and the suburbs. This research aims to summarize the experience of the coastal city in the process of sustainable development by analyzing the dynamic trends and driving factors of land use spatial and temporal changes in the target area so that it provides a reference for the long-term development of the city. Meanwhile, it also hopes to give support for refining and improving the spatiotemporal analysis method for sustainable urban land use through the experiment. Due to the appearance of the results of the abnormal data, in the experiment process, this article adopts a comparative experiment to avoid the error of the analysis result and to find out the reason. The results show that the urban area for construction increased rapidly in the past twenty years, which is mainly affected by factors, such as economic development, policy guidance, environmental awareness, and environmental protection measures, especially guided by policies. Thus, coastal cities should stretch the planning of sustainable development from the three aspects combining with local characteristics. Besides, phenological phenomena and crops harvest time tremendously affect the images and calculation. The selection of remotely-sensed images should fully consider the characteristics of urban and rural locations, especially the impact of local phenological phenomena. The results of the analysis provide reference value and support for sustainable urban land management and development in the study area and other coastal cities
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