Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking

Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.Comment: 91 pages, 67 figures, 11 tables. Related to the conference presentation D. Nikonov and I. Young, Uniform Methodology for Benchmarking Beyond-CMOS Logic Devices, Proceedings of IEDM, 25.4 (2012

Material Targets for Scaling All Spin Logic

All-spin logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to non-volatility, ultra-low operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin logic devices that can surpass energy-delay performance of CMOS transistors. With validated stochastic nano-magnetic and vector spin transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identified promising new directions for material engineering/discovery focusing on systematic scaling of magnetic anisotropy (Hk) with saturation magnetization (Ms), use of perpendicular magnetic anisotropy, and interface spin mixing conductance of ferromagnet/spin channel interface (Gmix). We provide systematic targets for scaling spin logic energy-delay product toward a 2 aJ.ns energy-delay product, comprehending the stochastic noise for nanomagnets.Comment: 21 pages, 8 figure

Circuit Theory for SPICE of Spintronic Integrated Circuits

We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We propose an extension to the Modified Nodal Analysis technique for the analysis of spin circuits based on the recently developed spin conduction matrices. We demonstrate the applicability of the framework using an example spin logic circuit described using spin Netlists.Comment: 14 pages, 11 figures; added fig. 2; added citations; modified title to emphasize SPICE; Results unchange

Patterns and Thresholds of Magnetoelectric Switching in Spin Logic Devices

In the quest to develop spintronic logic, it was discovered that magnetoelectric switching results in lower energy and shorter switching time than other mechanisms. Magnetoelectric (ME) field due to exchange bias at the interface with a multi-ferroic (such as BiFeO3) is well suited for 180 degree switching of magnetization. The ME field is determined by the direction of canted magnetization in BiFeO3 which can point at an angle to the plane, to which voltage is applied. Dependence of switching time and the threshold of ME field on its angles was determined by micromagnetic simulations. Switching occurs by formation of a domain wall on the side of the nanomagnet on top of BFO and its propagation to the rest of the magnet. For in-plane magnetization, switching occurs over a wide range of angles and at all magnitudes of ME field above threshold. For out-of-plane magnetization failure occurs (with an exception of a narrow range of angles and magnitudes of ME field) due to the domain wall reflecting from the opposite end of the nanomagnet.Comment: 7 pages, 5 figure

All Spin Nano-magnetic State Elements

We propose an all spin state element to enable all spin state machines using spin currents and nanomagnets. We demonstrate via numerical simulations the operation of a state element a critical building block for synchronous, sequential logic computation. The numerical models encompass Landau-Lifshitz-Gilbert (LLG) nanomagnet dynamics with stochastic models and vector spin-transport in metallic magnetic and non-magnetic channels. Combined with all spin combinatorial logic, the state elements can enable synchronous and asynchronous computing elements.Comment: 21 pages, 6 figure

Voltage and Energy-Delay Performance of Giant Spin Hall Effect Switching for Magnetic Memory and Logic

In this letter, we show that Giant Spin Hall Effect (GSHE) MRAM can enable better energy- delay and voltage performance than traditional MTJ based spin torque devices at scaled nanomagnet dimensions (10-30 nm). Firstly, we derive the effect of dimensional scaling on spin injection efficiency, voltage-delay and energy-delay of spin torque switching using MTJs and GSHE and identify the optimum electrode geometry for low operating voltage (10 GHz) operation. We show that effective spin injection efficiency >100 % can be obtained using optimum spin hall electrode thickness for 30 nm nanomagnet widths. Finally, we derive the energy-delay trajectory of GSHE and MTJ devices to calculate the energy-delay product of GSHE and MTJ devices with an energy minimum at the characteristic time of the magnets. Optimized GSHE devices when combined with PMA can enable MRAM with scaled nanomagnets (30 nm X 60 nm), ultra-low voltage operation (< 0.1 V), fast switching times (10 ps) and switching energy as low as 100 aJ/bit.Comment: 16 pages, 5 figure

Convolutional Networks for Image Processing by Coupled Oscillator Arrays

A coupled oscillator array is shown to approximate convolutions with Gabor filters for image processing tasks. Pixelated image fragments and filter functions are converted to voltages, differenced, and input into a corresponding array of weakly coupled Voltage Controlled Oscillators (VCOs). This is referred to as Frequency Shift Keying (FSK). Upon synchronization of the array, the common node amplitude provides a metric for the degree of match between the image fragment and the filter function. The optimal oscillator parameters for synchronization are determined and favor a moderate value of the Q-factor.Comment: 23 pages, 12 figure

Response to Comment on 'Spin-Orbit Logic with Magnetoelectric Nodes: A Scalable Charge Mediated Nonvolatile Spintronic Logic' (arXiv:1607.06690)

In this technical note, we address the comments on the energy estimates for Magnetoelectric Spin-orbit (MESO) Logic, a new logic device proposed by the authors. We provide an analytical derivation of the switching energy, and support it with time-domain circuit simulations using a self-consistent ferroelectric (FE) compact model. While the energy to charge a capacitor is dissipated in the interconnect and transistor resistance, we note that the energy to switch a capacitor and a FE is independent of the interconnect resistance value to the first order. Also device design can mitigate the parasitic energy losses. We further show the circuit simulations for a sub 10 aJ switching operation of a MESO logic device comprehending: a) Energy stored in multiferroic; b) Energy dissipation in the resistance of the interconnect, Ric ; c) Energy dissipation in the inverse spin-orbit coupling (ISOC) spin to charge converter Risoc; d) Supply, ground resistance, and transistor losses. We also identify the requirements for the resistivity of the spin-orbit coupling materials and address the effect of internal resistance of the spin to charge conversion layer. We provide the material parameter space where MESO (with a fan-out of 1 and interconnect) achieves sub 10 aJ switching energy with path for scaling via ferroelectric/magnetoelectric/spin-orbit materials development.Comment: we address the comments from arXiv:1607.06690 on the energy of MESO logic. The typical ISOC internal resistance should read 10k.Ohm. The technical note is 25 pages, 7 figure

Nanomagnetic Logic and Magnetization Switching Dynamics in Spin Torque Majority Gates

Spin torque majority gates are modeled and several regimes of magnetization switching (some leading to failure) are discovered. The switching speed and noise margins are determined for STMGs and an adder based on it. With switching time of 3ns at current of 80uA, the adder computational throughput is comparable to that of a CMOS adder.Comment: 4 pages, 14 figures, IEEE International Magnetic Conference Technical Digest, BT-08 (2012

Overcoming thermal noise in non-volatile spin wave logic

Spin waves are propagating disturbances in magnetically ordered materials, analogous to lattice waves in solid systems and are often described from a quasiparticle point of view as magnons. The attractive advantages of Joule-heat-free transmission of information, utilization of the phase of the wave as an additional degree of freedom and lower footprint area compared to conventional charge-based devices have made spin waves or magnon spintronics a promising candidate for beyond-CMOS wave-based computation. However, any practical realization of an all-magnon based computing system must undergo the essential steps of a careful selection of materials and demonstrate robustness with respect to thermal noise or variability. Here, we aim at identifying suitable materials and theoretically demonstrate the possibility of achieving error-free clocked non-volatile spin wave logic device, even in the presence of thermal noise and clock jitter or clock skew.Comment: 31 pages including supplementary informatio