27 research outputs found

    Fractalkine expression and the recruitment of CX3CR1+ cells in the prolonged mesangial proliferative glomerulonephritis

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    Fractalkine expression and the recruitment of CX3CR1+ cells in the prolonged mesangial proliferative glomerulonephritis.BackgroundWe established the reversible and the prolonged models of mesangial proliferative glomerulonephritis (GN) with anti-Thy 1 antibody 1-22-3. However, the essential factors leading to the prolonged glomerular alterations have not been identified.MethodsThe expressions of several chemokines and cytokines were compared in the reversible and the prolonged models. Expression of fractalkine and the number of the fractalkine receptor CX3CR1-positive cells in the glomeruli in the prolonged model were significantly higher than those in the reversible model. Then, the localization of fractalkine and the characteristics of CX3CR1+ cells were analyzed in glomeruli. To elucidate the significance of the fractalkine expression, we analyzed the expression in the model treated with angiotensin II receptor antagonist, candesartan.ResultsImmunostaining of fractalkine was detected on endothelial cells on the fifth day, and fractalkine staining also was detected in the mesangial area on day 14. Major parts of the CX3CR1+ cells in the glomeruli were macrophages, especially ED3+ cells. Candesartan treatment ameliorated the glomerular morphological findings at six weeks after disease induction. Although the treatment did not ameliorate the morphological finding at two weeks, decreased expression of fractalkine and CX3CR1+ were already detected at two weeks in rats treated with candesartan.ConclusionsFractalkine expression and the recruitment of CX3CR1+ cells in glomeruli might play an important role in the development of the prolonged disease. These expressions could be predictors of the prolonged disease of the mesangial proliferative glomerulonephritis

    Random Number Generation in Large-Scale Monte Carlo Calculations

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    Future of supercomputing

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    Efficient Implementation of the Multigrid Preconditioned Conjugate Gradient Method on Distributed Memory Machines

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    A multigrid preconditioned conjugate gradient (MGCG) method[15], which uses the multigrid method as a preconditioner for the CG method, has a good convergence rate even for the problems on which the standard multigrid method does not converge efficiently. This paper considers a parallelization of the MGCG method and proposes an efficient parallel MGCG method on distributed memory machines. For the good convergence rate of the MGCG method, several difficulties in parallelizing the multigrid method are successfully settled. Besides, the parallel MGCG method on Fujitsu multicomputer AP1000[8] has high performance and it is more than 10 times faster than the Scaled CG (SCG) method[6]. 1 Introduction Parallelization of the multigrid method has been studied and several parallel multigrid methods have been implemented. One natural parallelization approach is governed by the grid partitioning principles. Sbosny[13] analyzed and implemented parallel multigrid method using the domain decomposit..

    4th KEK Summer School

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    The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis

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    We propose the Ensparsed LU decomposition (ELU) method as a linear solver for large-scale circuit transient analysis. Ensparsing is an algorithmic technique of ignoring small values in computation. While some researchers have used ensparsing by value in linear solvers for circuit simulation, the ELU method incorporates ensparsing by time as well. A high performance implementation of the ELU method for transient analysis is also investigated. The ELU method is faster than the conventional linear solvers, and the advantages of the ELU method will still increase for larger circuits. I. INTRODUCTION As the progress of the VLSI technology, more delicate effects of electronic circuits become significant, and the importance of analog simulation is increasing. Circuit simulation is introduced into the board level design, where the clock rate and the slew rate become faster, and the detailed analog behavior of the circuit must be controlled. Circuit simulators are also used for circuit verifi..
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