Energy-efficient Key-equation Solving Algorithm for BCH Decoding

This paper presents an energy-efficient method to solve the key equation in BCH decoding. The key-equation solving block is so complicated that it consumes lots of energy because of multiple registers being dynamically updated every cycle. The block dominates the overall energy dissipation of strong BCH decoding and induces unwanted hotspots. In achieving a high-performance BCH decoder, an energy-efficient algorithm should be developed for solving the key equation. This paper proposes a novel method to detect the case of single error by exploiting the relation among syndromes. If a single-error case is detected, the modified error-locator polynomial is obtained without solving the key-equation. For a (16383, 15543, 60) decoder implemented in a 130nm CMOS process, the proposed method saves 99% and 91% of energy compared to the conventional algorithm and the previous method that detects the error-free case, respectively.11Nsciescopuskc

IMPLEMENTATION OF DIGITAL SIGNAL PROCESSING WITH HIGH DATA RATE SENSORS FOR DATA COMPRESSION

The onboard telemetry system of Korea Space Launch Vehicle-II (KSLV-II) acquires acoustic, vibration, and piezoelectric pressure sensors that require high data rate over several kilo samples per second, so the compression method is needed to expand link margin of telemetry system. This paper implements third-octave and FFT signal processing algorithms to reduce sensor data with high compression ratio depends on data acquisition requirements. The developed signal processing hardware module is composed of analog signal conditioning block and digital signal processing block on FPGA, and the digital block is fully implemented with dedicated hardware using HDL. For digital hardware implementation, multistage structure with ANSI standard octave filter bank is used for third-octave processing, and pipelined architecture is used for FFT. The performance of data acquisition and signal processing is evaluated and compared to the commercial data acquisition equipment.International Foundation for TelemeteringProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection

건강한 모바일 스토리지를 위한 초저전력 오류정정 시스템

2

Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA

This paper presents a fast method to extract logic functions of look-up tables (LUTs) from a bitstream in Xilinx FPGAs. In general, FPGAs utilize LUTs as a primary resource to realize a logic function, and a typical N-input LUT comprises 2N 1-bit SRAM and N – 1 multiplexers. Whereas the previous research demands 2N exhaustive processing to find a mapping rule between an LUT and a bitstream, the proposed method decreases the processing to 2N by eliminating unnecessary processing. Experimental results show that the proposed method can reduce reversing time by more than 57% and 85% for Xilinx Spartan-3 and Virtex-5 compared to the previous exhaustive algorithm. It is noticeable that the reduction time becomes more significant as a commercial Xilinx FPGA tends to include a more tremendous number of LUTs

Area-Efficient Early-Termination Technique for Belief-Propagation Polar Decoders

Early-termination techniques for a belief-propagation (BP) decoder of polar codes can improve the decoding throughput by finishing a decoding iteration when an early-termination condition is satisfied. In the BP decoders, the early-termination condition plays an important role, as it affects decoding iteration savings. In this letter, an area-efficient early-termination criterion is proposed, which simplifies the previous threshold-based termination condition by completely eliminating redundant computations. According to the experimental results, the proposed structure for (1024, 512) polar codes can reduce 72.7%, 66.5%, and 59.7% of hardware resources without any degradation in the error-correction performance and decoding throughput compared to the previous threshold-based, information-BER (bit error rate)-based, and frozen-BER-based early-termination techniques, respectively

RS 부호를 위한 저면적 신드롬 연산기

2

BCH 부호를 위한 저전력 에너지 키-방정식 풀이 알고리즘

2

6.4Gb/s multi- threaded BCH encoder and decoder for multi-channel SSD controllers

1

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism

Achieving the attractive error-correcting capability with a simple decoder structure, the polar code using successive cancellation (SC) decoding is now expected to be installed at the resource-limited IoT or embedded communications. However, the existing SC decoders normally suffer from the long processing latency caused by the serialized processing steps, limiting the practical applications of polar codes. In this article, to solve this latency problem, we present a new low-complexity merging operation that can increase the number of parallel factors for realizing the tree-level parallelism. We also modify the previous pruning method to further reduce the number of visited nodes at the parallel SC decoding scenario. In addition, a novel parallel partial-sum calculator (PSC) architecture is introduced to update partial-sum registers with multiple decoded bits by taking only one processing cycle. Implementation results show that the proposed 8-parallel SC polar decoder in 28-nm CMOS requires only 0.140 mu s to decode a (1024, 512) codeword of 5C system, remarkably reducing the decoding latency when compared to the state-of-the-art designs.11Nsciescopu