Comprehensive modeling and formulation of split DC link capacitors balancing problem in Three-Phase Three-Level bidirectional AC/DC converters operating with arbitrary power factor

Three-phase three-level AC/DC and DC/AC converters have demonstrated several advantages over their classical two-level counterparts such as better efficiency, enhanced total harmonic distortion, lower dv/dt and lesser overall chip area. T-type and neutral point clamped (NPC) topologies dominate the family of three-phase three-level converters, widely used in 10kVA – 100kVA power range. However, control of three-level converters is more complicated than of their classical two-level counterparts due to necessity of adopting an additional voltage loop, aimed to balance partial split DC link voltages. Moreover, the latter contain multiples of triple-base-frequency harmonic ripple even under balanced AC-side operation (this does not happen in two-level converters), which should be minimized by the balancing loop mentioned above. The nature of partial DC link ripple formation was analyzed in-depth for unity power factor operation, yet hardly extended to non-unity power factor cases. Moreover, inaccurate conclusions were drawn in some of the related studies. Consequently, this paper focuses on comprehensive modeling and formulation of split DC link capacitors balancing problem in three-phase three-level bidirectional AC/DC converters operating with arbitrary power factor. Analytical expression for dynamics of partial DC link voltages difference is derived and studied in depth. The relation between zero-sequence component of modulation signals and neutral point current, tending to unbalance partial DC link voltages is explicitly established for arbitrary power factor values. Practical cases of restricted and unrestricted zero-sequence component of modulation signals are presented. Analytical predictions are shown to be fully supported by simulations based on both switching-cycle-averaged and full switched converter models. Experimental results obtained employing a 10kVA T-type converter prototype operating with restricted zero-sequence component of modulation signals under different power factor values are also given to further validate the presented methodology

Baseline for Split DC Link Design in Three-Phase Three-Level Converters Operating with Unity Power Factor Based on Low-Frequency Partial Voltage Oscillations

The study sets a baseline for split DC link capacitance values and voltage set points in three-phase three-level AC/DC (or DC/AC) converters operating with unity power factor. In order to equalize the average values of partial DC link voltages, the controller generates a zero-sequence containing DC components only while employing neither dedicated DC link capacitance balancing hardware nor high-order zero-sequence component injection. Such a baseline is required in order to evaluate the effectiveness of different DC link capacitance reduction methods proposed in the literature. Unlike most previous works, utilizing neutral point current based on cumbersome analytical expressions to determine neutral point potential oscillations, the instantaneous power balance-based approach is employed in this paper, resulting in greatly simplified and more intuitive expressions. It is demonstrated that while the total DC link voltage is low-frequency ripple-free under unity power factor balanced AC-side operation, split DC link capacitors absorb triple-fundamental frequency power components with one-sixth load power magnitude. This yields significant opposite phase partial voltage ripples. In such a case, selection of DC link capacitances and voltage set points must take into account the expected values of AC-side phase voltage magnitude and split DC link capacitor voltage and current ratings. Simulation and experimental results validate the proposed methodology by application to a 10 kVA T-type converter prototype

Baseline for Split DC Link Design in Three-Phase Three-Level Converters Operating with Unity Power Factor Based on Low-Frequency Partial Voltage Oscillations

The study sets a baseline for split DC link capacitance values and voltage set points in three-phase three-level AC/DC (or DC/AC) converters operating with unity power factor. In order to equalize the average values of partial DC link voltages, the controller generates a zero-sequence containing DC components only while employing neither dedicated DC link capacitance balancing hardware nor high-order zero-sequence component injection. Such a baseline is required in order to evaluate the effectiveness of different DC link capacitance reduction methods proposed in the literature. Unlike most previous works, utilizing neutral point current based on cumbersome analytical expressions to determine neutral point potential oscillations, the instantaneous power balance-based approach is employed in this paper, resulting in greatly simplified and more intuitive expressions. It is demonstrated that while the total DC link voltage is low-frequency ripple-free under unity power factor balanced AC-side operation, split DC link capacitors absorb triple-fundamental frequency power components with one-sixth load power magnitude. This yields significant opposite phase partial voltage ripples. In such a case, selection of DC link capacitances and voltage set points must take into account the expected values of AC-side phase voltage magnitude and split DC link capacitor voltage and current ratings. Simulation and experimental results validate the proposed methodology by application to a 10 kVA T-type converter prototype

On the Minimum Value of Split DC Link Capacitances in Three-Phase Three-Level Grid-Connected Converters Operating with Unity Power Factor with Limited Zero-Sequence Injection

This paper introduces an approach to calculating the minimum value of split DC link capacitance in three-phase three-level grid-connected DC-AC converters operating with unity power factor without either active balancing circuits or AC zero sequence injection. Due to the fact that partial DC link voltages and rectified mains phase voltages reach their maximum and minimum values, respectively, at different time instants, it is feasible to decrease the minimum value of the former below the maximum value of the latter while still maintaining proper functionality of the power stage. The minimum possible split DC link capacitance values are hence derived from the boundary condition where the above-mentioned voltages are tangent to each other. The accuracy of the analytical derivations is confirmed by simulations and experiments carried out on a 10 kVA T-type converter prototype, which show a high degree of agreement