Design and simulation of a RF MEMS shunt switch for Ka and V bands and the impact of varying its geometrical parameters

RF MEMS plays an important role in microwave switching. The high performance of RF MEMS shunt such as high bandwidth, low insertion loss, and high isolation have made these switches well suitable for high performing microwave and millimeter wave circuits. This paper presents a RF MEMS shunt capacitive switch for Ka and V band application. This paper investigates the effect of various geometrical parameters on RF characteristics of the switch. The simulation results are presented and discussed.<br /

Design and simulation of a low voltage wide band RF MEMS switch

This paper presents design of an electrostatic wide band shunt capacitive coupling RF MEMS switch with low actuation voltage. The key factors of the RF MEMS switch design are the proper scattering parameters, low actuation voltage, and the cost of the fabrication process. An overview of the recent low actuation voltage RFMEMS switches has been presented. These designs still suffer from the complexity of process, lack of reliability, limitation of frequency band, and process cost. RF characteristics of a shunt RF MEMS switches are specified mostly by coupling capacitor in upstate position of the membrane Cu. This capacitor is in trade-off with actuation voltage. In this work, the capacitor is eliminated by using two short high impedance transmission lines, at the input and output of the switch. The simulation results demonstrate an improvement in the RF characteristic of the switch.<br /

Characterization and optimization to improve uneven surface on MEMS bridge fabrication

This paper presents an optimized fabrication method for developing a freestanding bridge for RF MEMS switches. In this method, the sacrificial layer is patterned and hard baked a 220&deg;C for 3min, after filling the gap between the slots of the coplanar waveguide. Measurement results by AFM and SEM demonstrate that this technique significantly improves the planarity of the sacrificial layer, reducing the uneven surface to less than 20nm, and the homogeneity of the Aluminum thickness across the bridge. Moreover, a mixture of O2, Ar and CF4 was used and optimized for dry releasing of the bridge. A large membrane (200&times;100&mu;m2) was released without any surface bending. Therefore, this method not only simplifies the fabrication process, but also improves the surface flatness and edge smoothness of the bridge. This fabrication method is fully compatible with standard silicon IC technology

PEMFC purging at low operating temperatures: An experimental approach

In this paper, the effect of operating temperature on optimal purge interval for maximum energy efficiency in a proton exchange membrane fuel cell (PEMFC) with dead-ended anode (DEA) was experimentally investigated. The study was conducted with a focus on challenges associated with operation at temperatures lower than the recommended designed temperature. With DEA, gradual voltage drop happens due to the accumulation of water and impurities such as nitrogen. Hence, periodic purging of the anode side is required to remove excess water and impurities that are accumulated at the anode side over time. Short purge intervals increase hydrogen loss that translates into low fuel utilisation, whereas long purge intervals result in voltage drop due to high water and impurity accumulations. Therefore, an optimal purge strategy should be implemented to maximise the stack energy efficiency. Depending on the operating conditions and loads, there are instances that a fuel cell stack operates at temperatures lower than its recommended designed temperature. Considering the temperature effect on the cell water management, operating temperature is an important factor to consider for optimising the purge strategy in PEMFCs. At lower operating temperatures (ie, below 50°C), more water is formed in liquid form, which makes the optimisation of purge strategy more challenging. For a stack temperature of 40°C, it was observed that with an increase in stack current from 0.25 to 0.45 A cm−2, the optimal purge interval decreases from 90 seconds to around 45 seconds, respectively. Increasing the stack temperature from 40°C to 50°C resulted in an increase in the optimal purge interval to 120 seconds and 90 seconds for stack currents of 0.25 (ie, low current density) and 0.45 A cm−2, respectively. At lower operating temperatures, more frequent purging schedules are needed accordingly to remove the liquid water from the cell. These results indicated that at lower