Low-Pressure CVD of Germanium-Silicon films using Silane and Germane sources

In this work a study of Low Pressure Chemical Vapour Deposition (LPCVD) of Germanium-Silicon films has been carried out. The films were deposited on thermally oxidised silicon wafers using a horizontal hot-wall LPCVD system, at deposition temperatures ranging from 430 to 480 oC and total pressures from 3 to 200 Pa. Pure GeH4 and SiH4 gas sources were used for the experiments. Growth kinetics and texture of GexSi1-x films versus varying deposition conditions, resulting in different film properties, were investigated. The effect of Germanium content in the layers on deposition rate at 430 oC and the change in the film crystallinity caused by deposition at different deposition pressures were studied

Breakdown and recovery of thin gate oxides

Breakdown events are studied in varying test set-ups with a high time resolution. Often a partial recovery from breakdown is observed\ud within a few ms. Parameters such as device area, stress conditions and parasitic elements prohibit the recovery if they result in a high system impedance. The results suggest the existence of a highly conductive path that can be annihilated during breakdown

Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Si0.7Ge0.3 Gate Material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si0.7 Ge0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory device

W-CMP for sub-micron inverse metallisation

Chemical Mechanical Polishing (CMP) of tungsten for an inverse metallisation scheme is investigated. The influence of CMP parameters on removal rate and uniformity is studied. The main effects on the removal rate are the applied pressure and the rotation rate of the polishing pad. To the first order Preston's equation is obeyed. The uniformity is best with equal rpm of pad and wafer and with perforated pads. Also, pattern density effects of CMP of W/PETEOS are investigated. Dishing increased at larger W-linewidth. Oxide erosion increased at larger pattern density and smaller W-linewidth. Electrical measurements on submicron (0.4 and 0.5 ¿m) test structures yielded good CMP results

Diffusion and electrical properties of Boron and Arsenic doped poly-Si and poly-GexSi1−x(x 0.3)Ge_xSi_1-x(x~0.3) as gate material for sub-0.25 µm complementary metal oxide semiconductor applications

In this paper the texture, morphology, diffusion and electrical (de‐) activation of dopants in polycrystalline GexSi1-x and Si have been studied in detail. For gate doping B+,BF2+ and As+ were used and thermal budgets were chosen to be compatible with deep submicron CMOS processes. Diffusion of dopants is different for GeSi alloys, B diffuses significantly more slowly and As has a much faster diffusion in GeSi. For B doped samples both electrical activation and mobility are higher compared to poly‐Si. Also for the first time, BF2+ data of doped layers are presented, these show the same trend as the B doped samples but with an overall higher sheet resistance. For arsenic doping, activation and mobility are lower compared to poly‐Si, resulting in a higher sheet resistance. The dopant deactivation due to long low temperature steps after the final activation anneal is also found to be quite different. Boron‐doped GeSi samples show considerable reduced deactivation whereas arsenic shows a higher deactivation rate. The electrical properties are interpreted in terms of different grain size, quality and properties of the grain boundaries, defects, dopant clustering, and segregation, and the solid solubility of the dopants

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Modelling of dishing for metal chemical mechanical polishing

In this paper, a physical model for the development of dishing during metal chemical mechanical polishing (CMP) is proposed. The main assumption of the model is that material removal occurs predominantly at the pad/wafer contacts. The distribution of pad/wafer contact size is studied first. This distribution is used as an input for a model of the dependence for the material removal rate on the line width. A relation that describes the development of dishing as a function of overpolish time will be presented. The model describes to a great accuracy the observed dishing effects, using one free paramete

Minority Carrier Tunneling and Stress-Induced Leakage Current for p+ gate MOS Capacitors with Poly-Si and PolySi0.7Ge0.3 Gate Material

In this paper the I-V conduction mechanism for gate injection (-V g), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -Vg of our devices. Time-to-breakdown data are presented and discusse