16,040 research outputs found

    Power Aware Learning for Class AB Analogue VLSI Neural Network

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    Recent research into Artificial Neural Networks (ANN) has highlighted the potential of using compact analogue ANN hardware cores in embedded mobile devices, where power consumption of ANN hardware is a very significant implementation issue. This paper proposes a learning mechanism suitable for low-power class AB type analogue ANN that not only tunes the network to obtain minimum error, but also adaptively learns to reduce power consumption. Our experiments show substantial reductions in the power budget (30% to 50%) for a variety of example networks as a result of our power-aware learning

    A bayesian analysis of beta testing

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    In this article, we define a model for fault detection during the beta testing phase of a software design project. Given sampled data, we illustrate how to estimate the failure rate and the number of faults in the software using Bayesian statistical methods with various different prior distributions. Secondly, given a suitable cost function, we also show how to optimise the duration of a further test period for each one of the prior distribution structures considered

    Energy storage in the UK electrical network : estimation of the scale and review of technology options

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    This paper aims to clarify the difference between stores of energy in the form of non-rechargeable stores of energy such as fossil-fuels, and the storage of electricity by devices that are rechargeable. The existing scale of these two distinct types of storage is considered in the UK context, followed by a review of rechargeable technology options. The storage is found to be overwhelmingly contained within the fossil-fuel stores of conventional generators, but their scale is thought to be determined by the risks associated with long supply chains and price variability. The paper also aims to add to the debate regarding the need to have more flexible supply and demand available within the UK electrical network in order to balance the expected increase of wind derived generation. We conclude that the decarbonisation challenge facing the UK electricity sector should be seen not only as a supply and demand challenge but also as a storage challenge. (c) 2010 Elsevier Ltd. All rights reserved

    Power scalable implementation of artificial neural networks

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    As the use of Artificial Neural Network (ANN) in mobile embedded devices gets more pervasive, power consumption of ANN hardware is becoming a major limiting factor. Although considerable research efforts are now directed towards low-power implementations of ANN, the issue of dynamic power scalability of the implemented design has been largely overlooked. In this paper, we discuss the motivation and basic principles for implementing power scaling in ANN Hardware. With the help of a simple example, we demonstrate how power scaling can be achieved with dynamic pruning techniques

    Mine and Thine: The Territorial Foundations of Human Property

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    Research shows that many animal species have morphological and cognitive adaptations for fighting with others to gain resources, but it remains unclear how humans make fighting decisions. Non-human animals often adaptively calibrate fighting behavior to ecological variables such as resource quantity and whether the resource is distributed uniformly or clustered in patches. Also, many species use strategies to reduce fighting costs such as resolving disputes based on power asymmetries or conventions. Here we show that humans apply an ownership convention in response to the problem of severe fighting. We designed a virtual environment where ten participants, acting as avatars, could forage and fight for electronic food items (convertible to cash). In the patchy condition, we observed an ownership convention—the avatar who arrives first is more likely to win—but in the uniform condition, where severe fighting is rare, the ownership convention is absent.

    On-chip timing measurement architecture with femtosecond resolution

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    A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185”m) in a 0.12”m CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date
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