Optimizations for real-time implementation of H264/AVC video encoder on DSP processor

International audienceReal-time H.264/AVC high definition video encoding represents a challenging workload to most existing programmable processors. The new technologies of programmable processors such as Graphic Processor Unit (GPU) and multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of H264/AVC video encoder on a single core among the six cores of TMS320C6472 DSP for Common Intermediate Format (CIF) (352x288) resolution is presented in order to move afterwards to a multicore implementation for standard and high definitions (SD,HD).Algorithmic optimization is applied to the intra prediction module to reduce the computational time. Furthermore, based on the DSP architectural features, various structural and hardware optimizations are adopted to minimize external memory access. The parallelism between CPU processing and data transfers is fully exploited using an Enhanced Direct Memory Access controller (EDMA). Experimental results show that the whole proposed optimizations, on a single core running at 700 MHz for CIF resolution, improve the encoding speed by up to 42.91%. They allow reaching the real-time encoding 25 f/s without inducing any Peak Signal to Noise Ratio (PSNR) degradation or bit-rate increase and make possible to achieve real time implementation for SD and HD resolutions when exploiting multicore features

Implantation de la chaîne de codage de la norme H.264 sur un processeur embarqué

International audienceCet article présente une implantation du processeur softcore MICROBLAZE sur un FPGA Spartan- 3 de Xilinx. L’application implantée est la chaîne de codage de la norme H.264, se manifestant en une transformée entière en cosinus discret (ICT), une quantification et la chaîne inverse, pour les images Intra prédites ayant pour application la vidéoconférence. Une étude théorique, des résultats d’implantation et de calcul de PSNR, sont également présentées dans cet article

Fast Prototyping H.264 Deblocking Filter Using ESL Tools

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Fast intra mode decision algorithm based on inter prediction mode for H264/AVC

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Real-time H.264/AVC baseline decoder implementation on TMS320C6416

International audienceThe H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720 MHz is obtained for Common Intermediate Format resolution (CIF 352 × 288

Fast Intra Mode Decision Algorithm for H264/AVC HD Baseline Profile Encoder

International audienceThe high performance of H.264/AVC video encoder is accompanied with a wide computation complexity especially for high definition (HD) video sequences. One of the major H.264/AVC features to be optimized is the mode decision for both inter and intra prediction. Thus, based on high correlation observed between selected inter prediction mode and intra mode decision, a fast intra mode decision algorithm based on the best inter prediction mode for H264 high definition (HD) baseline profile encoder is proposed. The evaluation of the proposed approach was based on the rate distortion and PSNR variation, execution time and percentage of skipping intra4x4 and intra16x16. The proposed scheme is performed on 720p (1280x720) and 1080p (1920x1088) HD video sequences. Experimental results show that the proposed algorithm can save up to 60% of intra prediction computation time, 16% of skipping intra16x16 and up to 83% for intra4x4 without inducing PSNR degradation and bit-rate increase. General Terms Video compression techniques and signal processing Keywords H264/AVC, Fast intra mode decision, High definition, baseline profile

Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC

International audienceMotion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA

Optimizations for real-time implementation of H264/AVC video encoder on DSP processor

International audienceReal-time H.264/AVC high definition video encoding represents a challenging workload to most existing programmable processors. The new technologies of programmable processors such as Graphic Processor Unit (GPU) and multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of H264/AVC video encoder on a single core among the six cores of TMS320C6472 DSP for Common Intermediate Format (CIF) (352x288) resolution is presented in order to move afterwards to a multicore implementation for standard and high definitions (SD,HD).Algorithmic optimization is applied to the intra prediction module to reduce the computational time. Furthermore, based on the DSP architectural features, various structural and hardware optimizations are adopted to minimize external memory access. The parallelism between CPU processing and data transfers is fully exploited using an Enhanced Direct Memory Access controller (EDMA). Experimental results show that the whole proposed optimizations, on a single core running at 700 MHz for CIF resolution, improve the encoding speed by up to 42.91%. They allow reaching the real-time encoding 25 f/s without inducing any Peak Signal to Noise Ratio (PSNR) degradation or bit-rate increase and make possible to achieve real time implementation for SD and HD resolutions when exploiting multicore features