Target density effects on charge tansfer of laser-accelerated carbon ions in dense plasma

We report on charge state measurements of laser-accelerated carbon ions in the energy range of several MeV penetrating a dense partially ionized plasma. The plasma was generated by irradiation of a foam target with laser-induced hohlraum radiation in the soft X-ray regime. We used the tri-cellulose acetate (C$_{9}$H$_{16}$O$_{8}$) foam of 2 mg/cm$^{-3}$ density, and $1$-mm interaction length as target material. This kind of plasma is advantageous for high-precision measurements, due to good uniformity and long lifetime compared to the ion pulse length and the interaction duration. The plasma parameters were diagnosed to be T$_{e}$=17 eV and n$_{e}$=4 $\times$ 10$^{20}$ cm$^{-3}$. The average charge states passing through the plasma were observed to be higher than those predicted by the commonly-used semiempirical formula. Through solving the rate equations, we attribute the enhancement to the target density effects which will increase the ionization rates on one hand and reduce the electron capture rates on the other hand. In previsous measurement with partially ionized plasma from gas discharge and z-pinch to laser direct irradiation, no target density effects were ever demonstrated. For the first time, we were able to experimentally prove that target density effects start to play a significant role in plasma near the critical density of Nd-Glass laser radiation. The finding is important for heavy ion beam driven high energy density physics and fast ignitions.Comment: 7 pages, 4 figures, 35 conference

An Innovative Implementation for Directory-based Cache Coherence in Shared Memory Multiprocessors

Directory-based cache coherence protocol is accepted as the common technique in large scale shared memory multiprocessors because of its scalability. Although it was extensively studied in the past, however, the memory overhead and long miss penalty entailed by this protocol are the major obstacles to scale for large scale multiprocessors. On the other hand, the ever-increasing cache line size makes the false sharing problem more serious than before, which will lead to high miss rate. Based on the scope consistency, we propose a lock-specific home-based cache coherence protocol. In this new cache coherence protocol, all directory memory overhead are eliminated completely and false sharing problem and high miss rate will be solved greatly at the cost of small write notice buffer in each processor. Keywords: Directory-based Cache Coherence Protocol, False Sharing, Scope Consistency, Memory Overhead. 1 Introduction Distributed Shared Memory(DSM) systems have gained popular acceptance by..

Reducing System Overheads in Home-based Software DSMs

Software DSM systems suffer from the high communication and coherence-induced overheads that limit performance. This paper introduces our efforts in reducing system overheads of a home-based software DSM called JIAJIA. Three measures, including eliminating false sharing through avoiding unnecessarily invalidating cached pages, reducing virtual memory page faults with a new write detection scheme, and propagating barrier message in a hierarchical way, are taken to reduce the system overhead of JIAJIA. Evaluation with some well-known DSM benchmarks reveals that, though varying with memory reference patterns of different applications, these measures can reduce system overhead of JIAJIA effectively

Sulforaphane (Sul) reduces renal interstitial fibrosis (RIF) by controlling the inflammation and TGF-β/Smad signaling pathway

Abstract All chronic renal disorders eventually lead to renal interstitial fibrosis (RIF). Chronic inflammation and pro-fibrotic substances are familiar companions of the fibrotic process. The Sulforaphane (Sul) molecule is particularly useful in protecting the liver from oxidative damage. To investigate the Sul effects on fibrosis markers and inflammatory proteins in the kidney of NRK52E cell line and rats and clarify the mechanism of TGF-β/Smad signaling pathway in a rat model of RIF were developed in the present study. Sul (50, 100, and 200 ng/ml) remarkably reduced the gene expressions of tumor necrosis factor (TNF-α), interleukin-6 (IL-6), interleukin (IL)-1β, collagen 3 (COL3A1), collagen 1 (COL1A1), and α-smooth muscle actin (α-SMA) in fibrotic NRK52E cells compared with those in cells inspired by transforming growth factor-α (TGF-α). Histopathological investigations showed that Sul administration retained renal tissue structure and decreased kidney tissue fibrosis in rats subjected to unilateral ureteral blockage (UUO). The expression level of TNF-α, IL-6, IL-1β, COL3A1, COL1A1, and α-SMA in the rats’ kidneys exposed to UUO was also suppressed by the treatment of Sul. In the present study, western blot analysis showed that Sul upregulated the expressions of fibrotic NRK52E cells Smad7 and rat model UUO groups while simultaneously decreasing the stimulation of Smad2/3 and the expressions of cyclooxygenase-2, NF-κB, Smad4, activator protein-1, and high-mobility group protein B1. Ultimately, Sul’s ability to inhibit the TGF-β/Smad pathway and the development of inflammation factors may mitigate RIF

An Innovative Implementation for Directory-based Cache Coherence in Shared Memory Multiprocessors

Directory-based cache coherence protocol is accepted as the common technique in large scale shared memory multiprocessors because of its scalability. Although it was extensively studied in the past, however, the memory overhead and long miss penalty entailed by this protocol are the major obstacles to scale for large scale multiprocessors. On the other hand, the ever-increasing cache line size makes the false sharing problem more serious than before, which will lead to high miss rate. Based on the scope consistency, we propose a lock-specific home-based cache coherence protocol. In this new cache coherence protocol, all directory memory overhead are eliminated completely and false sharing problem and high miss rate will be solved greatly at the cost of small write notice buffer in each processor. Keywords: Directory-based Cache Coherence Protocol, False Sharing, Scope Consistency, Memory Overhead. 1 Introduction Distributed Shared Memory(DSM) systems have gained popular acceptance by..

Reducing System Overheads in Home-based Software DSMs

Software DSM systems suffer from the high communication and coherence-induced overheads that limit performance. This paper introduces our efforts in reducing system overheads of a home-based software DSM called JIAJIA. Three measures, include eliminating false sharing through avoiding unnecessarily invalidating of cached pages, reducing virtual memory page faults with a new write detection scheme, and propagating barrier message in a hierarchical way, are taken to reduce the system overhead of JIAJIA. Evaluation with some well-known DSM benchmarks reveals that, though varying with memory reference patterns of different applications, these measures can reduce system overhead of JIAJIA effectively. 1 Introduction Software DSMs suffer from the high communication and coherence-induced overheads that limit performance. The communication cost of software DSMs is evidently high, large granularity of coherence causes problems of false sharing, encoding and decoding diffs in multiple writer ..

An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems

Coherence protocols and memory consistency models are two important issues in hardware coherent shared memory multiprocessors and software distributed shared memory(DSM) systems. Over the years, many researchers have made extensive study on these two issues respectively. However, the interaction between them has not been studied in the literature. In this paper, we study the coherence protocols and memory consistency models used by hardware and software DSM systems in detail. Based on our analysis, we draw a general definition for memory consistency model, i.e., memory consistency model is the logical sum of the ordering of events in each processor and coherence protocol. We also point that in hardware DSM system the emphasis of memory consistency model is relaxing the restriction of event ordering, while in software DSM system, memory consistency model focuses mainly on relaxing coherence protocol. Taking Lazy Release Consistency(LRC) as an example, we analyze the relationsh..

A Framework of Memory Consistency Models

Previous descriptions of memory consistency models in shared-memory multiprocessor systems are mainly expressed as constraints on the memory access event ordering and hence are hardware-centric. This paper presents a framework of memory consistency models which describes the memory consistency model on the behavior level. Based on the understanding that the behavior of an execution is determined by the execution order of conflicting accesses, a memory consistency model is defined as an interprocessor synchronization mechanism which orders the execution of operations from different processors. Synchronization order of an execution under certain consistency model is also defined. The synchronization order, together with the program order, determines the behavior of an execution