Accurate Modeling of the Effects of Fringing Area Interface Traps on Scanning Capacitance Microscopy Measurement

Scanning capacitance microscopy (SCM) is a dopant profile extraction tool with nanometre spatial resolution. While it is based on the high-frequency MOS capacitor theory, there are crucial second-order effects which make the extraction of dopant profile from SCM data a challenging task. Due to small size of the SCM probe, the trapped charges in the interface traps at the oxide-silicon dioxide interface surrounding the probe significantly affect the measured SCM data through the fringing electric field created by the trapped charges. In this paper, we present numerical simulation results to investigate the nature of SCM dC/dV data in the presence of interface traps. The simulation takes into consideration the traps response to the ac signal used to measure dC/dV as well as the fringing field of the trapped charge surrounding the probe tip. In the study, we present an error estimation of experimental SCM dopant concentration extraction when the interface traps and fringing field are ignored. The trap distribution in a typical SCM sample is also investigated

First-Principles Study of Point Defects in LaAlO₃

In this study, the native point defects including oxygen vacancy and interstitial, metal (La, Al) vacancy and interstitial, and metal antisite in perovskite LAO are studied. Defect formation energies are studied as a function of the external chemical potentials and Fermi level. The stable defects are identified under different external chemical potentials and Fermi levels. The effect of image charge corrections is also investigated. Finally, based on results in this study, optimal growth conditions can be proposed to achieve better defect engineering for LAO gate dielectrics.Singapore-MIT Alliance (SMA

Native Point Defects in yttria as a High-Dielectric-Constant Gate Oxide Material: A First-Principles Study

Yttria (Y₂O₃) has become a promising gate oxide material to replace silicon dioxide in metal-oxide-semiconductor (MOS) devices. The characterization of native point defect in Y₂O₃ is essential to understand the behavior of the material. We used the first-principles pseudopotential method to study the electronic structure, defect structure and formation energy of native point defects in Y₂O₃. Vacancies, interstitials and antisites in their relevant charge states are considered. The dominant defect types are identified under different chemical potentials and different Fermi levels. Oxygen vacancies are the dominant defect types under high yttrium chemical potential condition. Lower yttrium chemical potential leads to oxygen interstitials and ultimately yttrium vacancies when Y₂O₃ is used as a high dielectric constant gate oxide material in MOS devices.Singapore-MIT Alliance (SMA

Oblique Angle Deposition of Germanium Film on Silicon Substrate

The effect of flux angle, substrate temperature and deposition rate on obliquely deposited germanium (Ge) films has been investigated. By carrying out deposition with the vapor flux inclined at 87° to the substrate normal at substrate temperatures of 250°C or 300°C, it may be possible to obtain isolated Ge nanowires. The Ge nanowires are crystalline as shown by Raman Spectroscopy.Singapore-MIT Alliance (SMA

The Influence of Analyser Geometry Effects in Scanning Electron Microscope Voltage Contrast Measurements

A computer simulation model used to study specimen dependent and analyser geometry dependent effects is described in this paper. With this model, the influence of the specimen dependent effect on quantitative voltage contrast measurements can be isolated from the analyser geometry dependent effect. Linearization error voltages in quantitative voltage contrast measurements arising from the individual influences of the specimen dependent and analyser geometry dependent effects are presented. The results show that the error component due to very narrow analysers dominate the total linearization error. The same situation arises when the voltage measurement point on the specimen is very near to the edge of the analyser

Study of Stress Evolution of Germanium Nanocrystals Embedded in Silicon Oxide Matrix

Germanium (Ge) nanocrystals had been synthesized by annealing co-sputtered SiO₂-Ge in N₂ and/or forming gas (90% N₂ + 10% H₂) at temperatures ranging from 700 to 1000°C from 15 to 60 min. It was concluded that the annealing ambient, temperature and time have a significant influence on the formation and evolution of the nanocrystals. We also showed that a careful selective etching of the annealed samples in hydrofluoric solution enabled the embedded Ge nanocrystals to be liberated from the Si oxide matrix. From the Raman results of the as-grown and the liberated nanocrystals, we established that the nanocrystals generally experienced compressive stress in the oxide matrix and the evolution of these stress states was intimately linked to the distribution, density, size and quality of the Ge nanocrystals.Singapore-MIT Alliance (SMA

Charge storage in nanocrystal systems: Role of defects?

Wet thermal oxidations of polycrystalline Si₀.₅₄Ge₀.₄₆ films at 600°C for 30 and 50 min were carried out. A stable mixed oxide was obtained for films that were oxidized for 50 min. For film oxidized for 30 min, however, a mixed oxide with Ge nanocrystallites embedded in the oxide matrix was obtained. A trilayer gate stack structure that consisted of tunnel oxide/oxidized polycrystalline Si₀.₅₄Ge₀.₄₆/rf sputtered SiO₂ layers was fabricated. We found that with a 30 min oxidized middle layer, annealing the structure in N₂ ambient results in the formation of germanium nanocrystals and the annealed structure exhibits memory effect. For a trilayer structure with middle layer oxidized for 50 min, annealing in N₂ showed no nanocrystal formation and also no memory effect. Annealing the structures with 30 or 50 min oxidized middle layer in forming gas ambient resulted in nanocrystals embedded in the oxide matrix but no memory effect. This suggests that the charge storage mechanism for the trilayer structure is closely related to the interfacial traps of the nanocrystals.Singapore-MIT Alliance (SMA

Fabrication of Highly Ordered Nanoparticle Arrays Using Thin Porous Alumina Masks

Highly ordered nanoparticle arrays have been successfully fabricated by our group recently using ultra-thin porous alumina membranes as masks in the evaporation process. The sizes of the nanoparticles can be adjusted from 5-10 nm to 200 nm while the spacing between adjacent particles can also be adjusted from several nanometers to about twice the size of a nanoparticle. The configuration of the nanoparticles can be adjusted by changing the height of the alumina masks and the evaporation direction. Due to the high pore regularity and good controllability of the particle size and spacing, this method is useful for the ordered growth of nanocrystals. Different kinds of nanoparticle arrays have been prepared on silicon wafer including semiconductors (e.g., germanium) and metals (e.g., nickel). The germanium nanoparticle arrays have potential applications in memory devices while the nickel catalyst nanoparticle arrays can be used for the growth of ordered carbon nanotubes.Singapore-MIT Alliance (SMA

Charge Storage Effect in a Trilayer Structure Comprising Germanium Nanocrystals

A metal-insulator-semiconductor (MIS) device with a trilayer insulator structure consisting of sputtered SiO₂ (~50nm)/evaporated pure germanium (Ge) layer (2.4nm)/rapid thermal oxide (~5nm) was fabricated on a p-type Si substrate. The MIS device was rapid thermal annealed at 1000°C. Capacitance-voltage (C-V) measurements showed that, after rapid thermal annealing at 1000°C for 300s in Ar, the trilayer device exhibited charge storage property. The charge storage effect was not observed in a device with a bilayer structure without the Ge middle layer. With increasing rapid thermal annealing time from 0 to 400s, the width of the C-V hysteresis of the trilayer device increased significantly from 1.5V to ~11V, indicating that the charge storage capability was enhanced with increasing annealing time. High-resolution transmission electron microscopy results confirmed that with increasing annealing time, the 2.4nm amorphous middle Ge layer crystallized gradually. More Ge nanocrystals were formed and the crystallinity of the Ge layer improved as the annealing time was increased. When the measurement temperature was increased from –50°C to 150°C, the width of the hysteresis of the MIS device reduced from ~10V to ~6V. This means that the charge storage capability of the trilayer structure decreases with increasing measurement temperature. This is due to the fact that the leakage current in the trilayer structure increases with increasing measurement temperature.Singapore-MIT Alliance (SMA

Nanocrystalline Ge Flash Memories: Electrical Characterization and Trap Engineering

Conventional floating gate non-volatile memories (NVMs) present critical issues for device scalability beyond the sub-90 nm node, such as gate length and tunnel oxide thickness reduction. Nanocrystalline germanium (nc-Ge) quantum dot flash memories are fully CMOS compatible technology based on discrete isolated charge storage nodules which have the potential of pushing further the scalability of conventional NVMs. Quantum dot memories offer lower operating voltages as compared to conventional floating-gate (FG) Flash memories due to thinner tunnel dielectrics which allow higher tunneling probabilities. The isolated charge nodules suppress charge loss through lateral paths, thereby achieving a superior charge retention time. Despite the considerable amount of efforts devoted to the study of nanocrystal Flash memories, the charge storage mechanism remains obscure. Interfacial defects of the nanocrystals seem to play a role in charge storage in recent studies, although storage in the nanocrystal conduction band by quantum confinement has been reported earlier. In this work, a single transistor memory structure with threshold voltage shift, Vth, exceeding ~1.5 V corresponding to interface charge trapping in nc-Ge, operating at 0.96 MV/cm, is presented. The trapping effect is eliminated when nc-Ge is synthesized in forming gas thus excluding the possibility of quantum confinement and Coulomb blockade effects. Through discharging kinetics, the model of deep level trap charge storage is confirmed. The trap energy level is dependent on the matrix which confines the nc-Ge.Singapore-MIT Alliance (SMA