Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for Realistic Circuit Simulation of VLSI Circuits

This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a processldevice simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented. 1