Configurable ring oscillator with controlled interconnections

Circuit solutions for physically unclonable functions (PUF) of a ring oscillator (RO) implementation for the purposes of digital devices identification, cryptographic keys and random numbers generation are considered. The effectiveness using configurable ROs (CROs) in PUF circuits is based not only on reducing of the hardware overhead of traditional RO PUFs, but also on the generation of output signals with unique frequencies, close in value in a case of the FPGA implementation. The proposed modification of the basic scheme of the CRO PUF, based on the XOR2 logic gates as controlled delay elements, allows to use a full set of input challenges instead of the basic scheme. It is shown that the delay value depends not only on the challenge, but also on the interconnect configuration of the structural elements of the CRO circuit. A time model of the modified CRO PUF is proposed, which analytically proves the influence of interconnects on the frequency of the generated signal, which was experimentally confirmed using the Xilinx Zynq-7000 FPGA. Based on this result, a new structure of PUF CRO with controlled interconnections is proposed

Transparent Memory Tests Based on the Double Address Sequences

An important achievement in the functional diagnostics of memory devices is the development and application of so-called transparent testing methods. This is especially important for modern computer systems, such as embedded systems, systems and networks on chips, on-board computer applications, network servers, and automated control systems that require periodic testing of their components. This article analyzes the effectiveness of existing transparent tests based on the use of the properties of data stored in the memory, such as changing data and their symmetry. As a new approach for constructing transparent tests, we propose to use modified address sequences with duplicate addresses to reduce the time complexity of tests and increase their diagnostic abilities

Synthesis of a Test Generator for a Built-In Self-Test Scheme

This paper presents a new algorithm for the automated synthesis of pseudo-random test patterns generators for Built-In Self Test schemes with a mixed test mode. The experimental results show an opportunity of using the given method on a design stage of circuits producing. In this paper it is shown that an appropriate selection of test pattern generator can significantly reduce the hardware requirements of deterministic part. 1

Physically unclonable functions based on a controlled ring oscillator

The problem of constructing a new class of physically unclonable functions (PUF) based on a controlled ring oscillator (CRO) has beeb solved. The relevance of the creation of CROPUF is associated with the active development of physical cryptography used for the purposes of identifying electronic products and generating cryptographic keys. It is shown that classical physically unclonable functions based on ring oscillators (ROPUF) are characterized by large hardware redundancy due to the need to implement a large number of ROs, since each bit of the response requires an independent pair of real ROs. At the same time ROPUFs are characterized by better statistical properties compared to PUFs of the arbiter type and do not require ideal symmetry and identity of implemented ROs. As an alternative to ROPUF, a new class of physically unclonable functions is proposed, namely, CROPUF, which uses controlled ring oscillators based on controlling the frequency of generated pulses without changing the functionality and structure of the oscillator. An important advantage of the CRO is a possibility of implementing on its basis a set of ROs, the number of which reaches 2m, where m is the number of stages of the oscillator, and each of them is determined by the submitted request. The three alternative structures for the proposed PUF, namely CROPUF1, CROPUF2 and CROPUF3   are considered. Their main advantages and disadvantages are shown, including in the case of two implementation options, namely on programmed logic (FPGA) and arbitrary logic (ASIC). As a basic option for implementation on FPGA, CROPUF2 is considered less prone to inter-chip and, more importantly, intra-chip dependence caused by the technological features of the production process. Practical studies were carried out by implementing CROPUF2 on modern FPGAs, evaluating its performance and its main characteristics. The operability of a new class of PUFs when implemented on programmable logic, as well as high rates of their main statistical characteristics, has been experimentally confirmed