19 research outputs found
Study of loss in superconducting coplanar waveguide resonators
Superconducting coplanar waveguide (SCPW) resonators have a wide range of
applications due to the combination of their planar geometry and high quality
factors relative to normal metals. However, their performance is sensitive to
both the details of their geometry and the materials and processes that are
used in their fabrication. In this paper, we study the dependence of SCPW
resonator performance on materials and geometry as a function of temperature
and excitation power. We measure quality factors greater than at
high excitation power and at a power comparable to that generated
by a single microwave photon circulating in the resonator. We examine the
limits to the high excitation power performance of the resonators and find it
to be consistent with a model of radiation loss. We further observe that while
in all cases the quality factors are degraded as the temperature and power are
reduced due to dielectric loss, the size of this effect is dependent on
resonator materials and geometry. Finally, we demonstrate that the dielectric
loss can be controlled in principle using a separate excitation near the
resonance frequencies of the resonator.Comment: Replacing original version. Changes made based on referee comments.
Fixed typo in equation (3) and added appendi
Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits
We review the salient features of two advanced nodes of an 8-Nb-layer fully
planarized process developed recently at MIT Lincoln Laboratory for fabricating
Single Flux Quantum(SFQ) digital circuits with very large scale integration on
200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is
tuned for energy efficient SFQ circuits. The former has eight superconducting
layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for
circuit resistors. The latter has nine superconducting layers: eight Nb wiring
layers with the minimum feature size of 350 nm and a thin superconducting MoNx
layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming
compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower
nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and
biasing of Josephson junctions. Another resistive layer is added to form
interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted
flux quanta from superconducting loops of logic cells. Both process nodes use
Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one
layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100
{\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by
248-nm photolithography and high density plasma etching. All circuit layers are
fully planarized using chemical mechanical planarization (CMP) of SiO2
interlayer dielectric. The following results and topics are presented and
discussed: the effect of surface topography under the JJs on the their
properties and repeatability, critical current and Jc targeting, effect of
hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high
kinetic inductance layer, technology of m{\Omega}-range resistors.Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented
on September 8, 2015 at the 12th European Conference on Applied
Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE
Transaction on Applied Superconductivity, 201
Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers
To increase density of superconductor digital and neuromorphic circuits by
10x and reach integration scale of Josephson junctions (JJs) per chip,
we developed a new fabrication process on 200-mm wafers, using self-shunted
Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a
layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers
and 2 layers of high kinetic inductance materials, MoN and NbN, with sheet
inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by
two methods: with =15.5 K by reactive sputtering of a Nb target in
Ar+N mixture; with in the range from 9 K to 13 K by plasma-enhanced
chemical vapor deposition (PECVD) using
Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of
NbN was investigated to obtain conformal deposition and filling narrow trenches
and vias with high depth-to-width ratios, which was not possible to achieve
using sputtering and other physical vapor deposition (PVD) methods at
temperatures below required to prevent degradation of Nb/Al-AlOx/Nb
junctions. Nb layers with 200 nm thickness are used in the process layer stack
as ground planes to maintain a high level of interlayer shielding and low
intralayer mutual coupling, for passive transmission lines with wave impedances
matching impedances of JJs, typically <=50 , and for low-value
inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb
bilayers and individual pattering of both layers to form inductors allowed us
to minimize parasitic kinetic inductance associated with interlayer vias and
connections to JJs as well as to increase critical currents of the vias.
Fabrication details and results of electrical characterization of NbN films,
wires, and vias, and comparison with Nb properties are given.Comment: 12 pages, 16 figures, 4 tables, 49 references. Submitted to IEEE TAS
on Nov. 10, 202
Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)
Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device
technology enables speed-of-light, nearly lossless communications to advance
cryogenic (4 K or lower) computing. However, the lack of large-area
superconducting IC has hindered the development of scalable practical systems.
Herein, we describe a novel approach to interconnect 16 high-resolution deep UV
(DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely
large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The
fabrication process starts by interconnecting four high-resolution DUV EX4 (22
mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line
(365 nm lithography) reticle, followed by I-line reticle stitching at the
boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88
mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and
maintained high-stitched line superconducting critical currents. We examined
quantum flux parametron (QFP) circuits to demonstrate the viability of common
active components used for data buffering and transmission. Considering that no
stitching requirement for high-resolution EX4 DUV reticles is employed, the
present fabrication process has the potential to advance the scaling of
superconducting quantum devices
Broadband Squeezed Microwaves and Amplification with a Josephson Traveling-Wave Parametric Amplifier
Squeezing of the electromagnetic vacuum is an essential metrological
technique used to reduce quantum noise in applications spanning gravitational
wave detection, biological microscopy, and quantum information science. In
superconducting circuits, the resonator-based Josephson-junction parametric
amplifiers conventionally used to generate squeezed microwaves are constrained
by a narrow bandwidth and low dynamic range. In this work, we develop a
dual-pump, broadband Josephson traveling-wave parametric amplifier that
combines a phase-sensitive extinction ratio of 56 dB with single-mode squeezing
on par with the best resonator-based squeezers. We also demonstrate two-mode
squeezing at microwave frequencies with bandwidth in the gigahertz range that
is almost two orders of magnitude wider than that of contemporary
resonator-based squeezers. Our amplifier is capable of simultaneously creating
entangled microwave photon pairs with large frequency separation, with
potential applications including high-fidelity qubit readout, quantum
illumination and teleportation