GaAs on Si epitaxy by aspect ratio trapping: analysis and reduction of defects propagating along the trench direction

The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, 8 108 cm 2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only on {111} Si planes, minimizing the interfacial energy and preventing the formation of antiphase boundaries

Backside and edge cleaning of III–V on Si wafers for contamination free manufacturing

III-V on Silicon epitaxial wafers are typically contaminated with residual III-V materials on the backside, bevel and front side exclusion zone. This contamination poses a risk for device manufacturing. The level of contamination can vary from trace to gross, depending on the epitaxial deposition process and method of backside wafer surface protection. Even when the backside surface is well protected and cleaned, trace amounts of III-V material including arsenic can still be detected. Wet clean methods usually use acid chemistries and if not optimized may involve significant chemical cost, safety risks, and contamination issues. Wafer backside and edge cleaning processes, employed to remove residual III-V material need to be designed for robust performance with a wide range of deposited materials and repeatable results in order to ensure contamination free manufacturing at subsequent steps of the fabrication flow

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

We report on the development of a metamorphic In0.53Ga0.47As-based heterostructure grown on 300 mm on-axis Si (001) wafers by metal-organic chemical vapor deposition (MOCVD), and the fabrication of a Metal-Oxide-Semiconductor Capacitor (MOSCAP) with C–V characteristics and interfacial trap density (Dit) values comparable to those of an equivalent structure grown on an InP substrate. A 1.15 µm thick GaAs/InP buffer with a defect density in the low 109 cm−2 range and a surface roughness rms value <2 nm was used to accommodate the large lattice mismatch between In0.53Ga0.47As and Si