Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Receiver Front-End Circuits for Future Generations of Wireless Communications

In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in low-noise amplifiers, mixers and oscillators are considered. The concepts derived are applied to a few classes of wireless communications standards that are broadband in nature at RF and/or require a broadband IF. Multi-mode, multi-band operation and adaptability as key requirements for future generation receivers are highlighted throughout the paper

Receiver front-end circuits for future generations of wireless communications

In this paper, new receiver concepts and CMOS circuits for future wireless communications applications are introduced. The concepts derived are applied to a few classes of wireless communications standards that are broad-band at radio frequencies and/or require a broad-band baseband circuitry. Multimode multiband operation and adaptivity as key requirements for future generation receivers are highlighted throughout the paper. The tradeoffs between power consumption, noise figure and linearity performance of low-noise amplifiers, mixers, and intermediate frequency filters are considered too

A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP

A low-power low-voltage wide-band inductor-less multi-standard receiver RF front-end in a digital CMOS 65nm Low Power (LP) process is described. S11 less than -10 dB is measured in the frequency range from 10MHz up to 5GHz. The front-end featuring two gain modes, achieves a voltage gain of 29dB in the high voltage gain mode, and a voltage gain of 23dB in the low voltage gain mode. The 3dB bandwidth of the RF front-end is 2.5GHz. The measured NF at 1GHz is 5.5dB in the high gain mode and 7.7dB in the low gain mode. The front-end achieves an IIP3 of -13.5dBm and -7.5dBm in the high and the low gain mode, respectively. It consumes 13 mA from a 1.2V supply in both gain modes. The implemented front-end occupies a chip area of 670um x 860)um

A reconfigurable low-noise amplifier using a tunable active inductor for multistandard receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S 21 (Gain) of 22 dB, S 11 of −18 dB, S 22 of −16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm2

A Gilbert Cell Mixer with Digitally Controlled Performance Space

In today’s world, new wireless communication standards evolve fast, putting a significant burden on set makers and RF IC design houses to have integrated and cheap solutions quickly on the market place. Hence there is a strong need for flexible circuit topologies that can support a range of applications via adjustability and configurability. However, this concept makes only sense if the reuse count (how many times the circuit is used while having a minimum amount of design effort) of the flexible circuits justifies the investment. This in turn, is strongly related to the performance space (the set of specifications that can be covered with one circuit, which is a sub-set of the total design space) that can be covered by the adjustable circuit. In order to assess this performance space, the Gilbert cell is considered as an example. The Gilbert cell is the most common switching mixer topology, and it is used as a basis for a digitally controlled Gilbert cell. Hence, design equations of the Gilbert cell are determined and a full design procedure is developed. DC limitations and design parameter limitations of the Gilbert cell are considered. The design space of the Gilbert cell for CMOS 0.25um technology, is determined. Following assessment of its limitations and its design space, a digitally controlled Gilbert cell is derived starting from the basic Gilbert cell. Some general solutions how the digitally controlled Gilbert might be used as a sheared component in multi-standard terminals, are mentioned. Advantages and drawbacks of these solutions in comparison with the fixed solutions are discussed