Towards the Automatic Design of More Efficient Digital Circuits

This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping to represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values. Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits can be explored. The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of two-input logic gates that in terms of number of two-input gates used is more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are XORs, and inversions (NOT). The evolved four-bit multiplier consists of two-input logic gates that is more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs

Scalability Problems of Digital Circuit Evolution - Evolvability and Efficient Designs

A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit. This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster..