Novel method of producing ultrasmall platinum silicide gate electrodes

\u3cp\u3eA novel method has been developed for producing platinum silicide gate electrodes with submicron width. A lateral chemical reaction of platinum with polycrystalline silicon at a step edge was used. The width of the wire is determined by the thickness of a sputtered metal layer. Wires with width between 35 and 300 nm have been produced. The method has been used for making long-channel field-effect transistors with good device properties. Some preliminary results of the study of the low-temperature electrical transport properties of inversion layers with width of 0.12 μm are reported.\u3c/p\u3

Method of manufacturing nanowires and electronic device

In the method, semiconductor substrates are etched to provide nanowires, said substrates comprising a first layer of a first material and a second layer of a second material with a mutual interface, which first and second materials are different. They may be different in the doping type. Alternatively, the main constituent of the material may be different, for example SiGe or SiC versus Si, or InP versus InAs. In the resulting nanowires, the interface is atomically sharp. The electronic devices having nanowires between a first and second electrode accordingly have very good electroluminescent and optoelectronic properties

Method of manufacturing nanowires and electronic device

In the method, semiconductor substrates are etched to provide nanowires, said substrates comprising a first layer of a first material and a second layer of a second material with a mutual interface, which first and second materials are different. They may be different in the doping type. Alternatively, the main constituent of the material may be different, for example SiGe or SiC versus Si, or InP versus InAs. In the resulting nanowires, the interface is atomically sharp. The electronic devices having nanowires between a first and second electrode accordingly have very good electroluminescent and optoelectronic properties

High-value MOS capacitor arrays in ultradeep trenches in silicon

\u3cp\u3eA fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm\u3csup\u3e2\u3c/sup\u3e.\u3c/p\u3

The influence of polysilicon gate morphology on dopant activation and deactivation kinetics in deep-submicron CMOS transistors

\u3cp\u3eIn this paper, the impact of gate microstructure on the activation and deactivation kinetics of ion-implanted dopants is discussed. A comparison is made between large-grained polysilicon that was obtained by recrystallizing deposited amorphous silicon, and fine-grained polysilicon. Very good gate activation was achieved for both As- and B-implanted fine-grained polysilicon gates using post-implant rapid thermal annealing for 20 s at 980-1010°C, leading to gate depletion levels below 5%. Similar levels of gate activation are found for spike annealing of 1 s at 1100°C. The kinetics of dopant deactivation in large- and fine-grained polysilicon have been measured in the temperature range from 700 to 800°C. From these measurements, the loss in the gate activation due to extra annealing steps in a 0.13 μm CMOS process flow has been evaluated. Silicidation is the most harmful process step leading to an increase in the gate depletion level to 6% for a p-type fine-grained polysilicon gate, representing the worst case situation. Finally, TSUPREM-4 gate depletion simulations for future CMOS generations (≤0.10 μm) have revealed the need of high dopant concentration (4-5 × 10\u3csup\u3e20\u3c/sup\u3e cm\u3csup\u3e-3\u3c/sup\u3e) which questions the possibility of polysilicon use as a gate material.\u3c/p\u3

Silicon based system-in-package:A new technology platform supported by very high quality passives and system level design tools

\u3cp\u3eThe very large development of home and domestic electronic appliances as well as portable device has led the microelectronics industry to evolve in two complimentary directions: More Moore with the continuous race towards extremely small dimensions hence the development of SoCs (System on Chip) and more recently a new direction that we could name More than Moore with the integration of devices that were laying outside the chips and thus the creation of SiPs (System in Package). The technology platform presented here is named Silicon Based System in Package. This new platform is based upon the integration of passive devices into Silicon. The four critical elements of this technology will be discussed in detail: passive integration, advanced packaging, new IC design development tools, and innovative testing..\u3c/p\u3

Ultrahigh capacitance density for multiple ALD-grown MIM capacitor stacks in 3-D silicon

Trench capacitors containing multiple metal-insulator-metal (MIM) layer stacks are realized by atomic-layer deposition (ALD), yielding an ultrahigh capacitance density of 440 nF/mm2 at a breakdown voltage VBD > 6 V. This capacitance density on silicon is at least 10 times higher than the values reported by other research groups. On a silicon substrate containing high-aspect-ratio macropore arrays, alternating MIM layer stacks comprising high-k Al2O3 dielectrics and TiN electrodes are deposited using optimized ALD processing such that the conductivity of the TiN layers is not attacked. Ozone annealing subsequent to each Al2O3 deposition step yields significant improvement of the dielectric isolation and breakdown properties