New low-stress PECVD poly-SiGe layers for MEMS

Thick poly-SiGe layers, deposited by plasma-enhanced chemical vapor deposition (PECVD), are very promising structural layers for use in microaccelerometers, microgyroscopes or for thin-film encapsulation, especially for applications where the thermal budget is limited. In this work it is shown for the first time that these layers are an attractive alternative to low-pressure CVD (LPCVD) poly-Si or poly-SiGe because of their high growth rate (100-200 nm/min) and low deposition temperature (520/spl deg/C-590/spl deg/C). The combination of both of these features is impossible to achieve with either LPCVD SiGe (2-30 nm/min growth rate) or LPCVD poly-Si (annealing temperature higher than 900/spl deg/C to achieve structural layer having low tensile stress). Additional advantages are that no nucleation layer is needed (deposition directly on SiO/sub 2/ is possible) and that the as-deposited layers are polycrystalline. No stress or dopant activation anneal of the structural layer is needed since in situ phosphorus doping gives an as-deposited tensile stress down to 20 MPa, and a resistivity of 10 m/spl Omega/-cm to 30 m/spl Omega/-cm. With in situ boron doping, resistivities down to 0.6 m/spl Omega/-cm are possible. The use of these films as an encapsulation layer above an accelerometer is shown

Stacked boron doped poly-crystalline silicon-germanium layers: an excellent MEMS structural material

In this work stacked boron doped poly-crystalline Silicon-Germanium (poly-SiGe) layers, which can be applied as structural MEMS layers, were studied. A standard 1 µm base layer, deposited at 480 ºC chuck temperature, is stacked until the required thickness (e.g. 10 x for a 10 µm thick layer). This 1 µm base layer consists of a PECVD seed layer (+/− 75 nm), a CVD crystallization layer (+/− 135 nm) and a PECVD layer to achieve the required thickness with a high growth-rate. The top part of this PECVD layer can optionally be used for optimizing the stress gradient by a stress compensation layer. This approach resulted in 4 µm thick poly-SiGe MEMS structural layers with low tensile stress (50 MPa), low resistivity (2 mΩcm) and a low strain gradient (< 1*10¯⁵/µm).status: publishe

SiGe MEMS technology: a platform technology enabling different demonstrators

In imec's 200mm fab a dedicated poly-SiGe above-IC MEMS (Micro Electro-Mechanical Systems) platform has been set up to integrate MEMS and its readout and driving electronics on one chip. In the Flemish project Gemini the possibilities of this platform have been further explored together with the project partners. Three different demonstrators were realized: mirrors for display applications, grating light valves (GLV) and accelerometers. Whereas the mirrors and GLVs are made with a similar to 300 nm thick SiGe structural layer plus optical coating, the SiGe structural layer thickness for the accelerometers is 4 mu m in order to improve the capacitive readout of in-plane devices. The processing and measurement results of these functional demonstrators are shown in this paper. These new demonstrators reconfirm the generic nature of the SiGe MEMS platform