Communication costs in a multi-tiered MPSoC

The amount of digital processing required for phased array beamformers is very large. It requires many parallel processors, which can be organized in a multi-tiered structure. Communication costs differ for each of the stages in such an architecture. For example, communication costs from the antenna front-end to the first processing stages is costly because of the amount of connections and data rate. Furthermore there is a trade-off between sequential processing exploiting locality of reference versus exploiting parallelism but adding communication costs. Thus, the optimal architecture depends on the importance that is given to the different measures.\ud \ud A model is presented to determine the partitioning of a (beamforming) system based on communication costs. It is shown that different solutions can be explored based on the cost model and the incorporated quantitative and qualitative measures. Determining the importance of each measure is subjective to the situation and application. In this work a simple beamforming application is used optimised for energy efficiency

Rationale for and design of a generic tiled hierarchical phased array beamforming architecture

The purpose of the phased array beamforming project is to develop a generic flexible efficient phased array receiver platform, using a mixed signal hardware/software-codesign approach. The results will be applicable to any radio (RF) system, but we will focus on satellite receiver (DVB-S) and radar applications. We will present a preliminary mapping of beamforming processing on a tiled architecture and determine its scalability.\ud \ud The functionality, size and cost constraints imply an integrated mixed signal CMOS solution. For a generic flexible multi-standard solution, a software defined radio approach is taken. Because a scalable and dependable solution is needed, a tiled hierarchical architecture is proposed with reconfigurable hardware to regain flexibility. A mapping is provided of beamforming on the proposed architecture. The advantages and disadvantages of each solution are discussed with respect to applicability and scalability.\ud \ud Different beamforming processing solutions can be mapped on the same proposed tiled hierarchical architecture. This provides a flexible, scalable and reconfigurable solution for a wide application domain. Beamforming is a data-driven streaming process which lends itself well for a regular scalable architecture. Beamsteering on the other hand is much more control-oriented and future work will focus on how to support beamsteering on the proposed architecture as well

Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation

Angular CMA: A modified Constant Modulus Algorithm providing steering angle updates

Conventional blind beamforming algorithms have no direct notion of the physical Direction of Arrival angle of an impinging signal. These blind adaptive algorithms operate by adjusting the complex steering vector in the case of changing signal conditions and directions. This paper presents Angular CMA, a blind beamforming method that calculates steering angle updates (instead of weight vector updates) to keep track of the desired signal. Angular CMA and its respective steering angle updates are particularly useful in the context of mixed-signal hierarchical arrays as means to find and distribute steering parameters. Simulations of Angular CMA show promising convergence behaviour, while having a lower complexity than alternative methods (e.g., MUSIC)

Leveraging academic knowledge in the innovation ecosystem

Scientific advancement and advancements in information technology have increased our capability for sharing information, and spreading scientific discoveries throughout society. In the past decade the Dutch government has been trying to stimulate the knowledge economy through various means. Among them the stimulation of the founding of the Dutch Centres for Entrepreneurship, and the Valorisation programme. However, over the years, publication volume has become the main indicator for being a successful scientist. This focus on publications and research disincentivizes scientists from activities that generate more concrete value for society. The Societal Impact Value Cycle seeks to offer scientists and others a toolbox for visualising and understanding the way innovation can be fostered, and how other processes can foster scientific research in return. It also maps the way by which an innovation ecosystem generates socio-economic value from academic activities. It should be noted that not all scientific research leads to innovations that generate value for society, and not all research is intended to change the course of events. Nonetheless, fostering cooperation between research institutes and societal stakeholders, and increasing awareness of how entrepreneurial skills and activities could not only lead to a return on investments necessary for scientific advancement, but also increase the societal impact from academic endeavours. This could benefit our society, and societies worldwide, both socially and economically. This publication will offer valuable insight and an effective toolbox for people interested in socio-economic value creation from scientific research, or, in other words, valorisation. Therewith, it lays at the heart of Stichting Maatschappij en Onderneming’s daily occupations and our close cooperation with the Erasmus University Rotterdam

Towards effective modeling and programming multi-core tiled reconfigurable architectures

For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modeling and programming such systems remains an issue. We will advocate a model-based design approach and propose a single semantic (programming) model for representing the specification, design and implementation. This approach tackles these problems at a higher conceptual level, thereby exploiting the inherent composability and parallelism available in the formalism. A case study illustrates the use of the semantic model with examples from analogue/digital co-design and hardware/software co-design

Personalities in female domesticated pigs: behavioural and physiological indications

The inconclusive evidence so far on the existence of distinct personality types in domesticated pigs, led us to perform the present experiment. A total of 128 gilts from 31 sows were systematically studied from birth to slaughter in two identical trials. Intra-test consistency in individual behavioural andror physiological reactions was studied in three different tests. We were not able to show consistencies in reactions of gilts over time to a backtest (at 2–4 days and 4 weeks of age) and to a novel environment test (at 10 and 24 weeks of age). Individual aggression, however, as measured in a group-feeding competition test in stable groups (at 10 and 24 weeks of age), proved to be highly consistent. Explanations for these discrepancies in intra-test consistencies are critically discussed. Inter-test consistencies were determined by relating the individual reactions of gilts to the backtest to various characteristics and responses to tests at a later age. The highest correlations were found when resistance in the first backtest was involved. No evidence was found for the existence of specific isolated categories of animals with respect to this resistance. For further analysis, extreme responding gilts in the first backtest (roughly the top and bottom 25% of the distribution) were classified as low resistant (LR; <3 escape attempts; n=31) or high resistant (HR; >4 escape attempts; n=45). By comparisons of mean responses of LR and HR gilts within groups, we have established a relationship between the backtest and several other variables. Behaviourally, the HR gilts showed more aggression in the group-feeding competition tests. Also, in the competition for the most productive teats at the anterior, a predominant position of HR piglets at this site was observed during the suckling period. The latter piglets also gained more weight during this period than LR ones. Compared to HR pigs, in the first novel environment test LR pigs hesitated longer to leave their home pens and to contact a human, but no difference in their locomotory behaviour was observed. Contrasts between LR and HR pigs in the second novel environment test were reduced or absent. Physiologically, when compared to HR gilts, LR ones had a higher reactivity of the hypothalamic–pituitary–adrenocortical (HPA) system. This was shown by higher cortisol responses to the first novel environment test, to routine weighing at 25 weeks of age, and to administration of a high dose of ACTH. It is discussed that these findings for LR and HR gilts, may provide support for the existence of behavioural and physiological responses in pigs, resembling those of proactive and reactive rodents.

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool