Neuromorphic photonics: 2D or not 2D?

The computing industry is rapidly moving from a programming to a learning area, with the reign of the von Neumann architecture starting to fade, after many years of dominance. The new computing paradigms of non-von Neumann architectures have started leading to the development of emerging artificial neural network (ANN)-based analog electronic artificial intelligence (AI) chipsets with remarkable energy efficiency. However, the size and energy advantages of electronic processing elements are naturally counteracted by the speed and power limits of the electronic interconnects inside the circuits due to resistor-capacitor (RC) parasitic effects. Neuromorphic photonics has come forward as a new research field, which aims to transfer the well-known high-bandwidth and low-energy interconnect credentials of photonic circuitry in the area of neuromorphic platforms. The high potential of neuromorphic photonics and their well-established promise for fJ/Multiply-ACcumulate energy efficiencies at orders of magnitudes higher neuron densities require a number of breakthroughs along the entire technology stack, being confronted with a major advancement in the selection of the best-in-class photonic material platforms for weighting and activation functions and their transformation into co-integrated photonic computational engines. With this paper, we analyze the current status in neuromorphic computing and in available photonic integrated technologies and propose a novel three-dimensional computational unit which, with its compactness, ultrahigh efficiency, and lossless interconnectivity, is foreseen to allow scalable computation AI chipsets that outperform electronics in computational speed and energy efficiency to shape the future of neuromorphic computing

WDM-Enabled Optical RAM at 5 Gb/s Using a Monolithic InP Flip-Flop Chip

We experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6×2 mm2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance

Monolithically integrated all-optical SOA-based SR Flip-Flop on InP platform

In this paper, we demonstrate for the first time a monolithically integrated InP All-Optical Flip-Flop (FF) based on optical coupled SOA-MZI switches. The experimental proof of principle demonstrated successful error free operation of SR-FF functionality at 5 Gb/s