Annealing effects on the loss and birefringence of silicon oxynitride rectangular optical waveguides

Author name used in this publication: M. S. DemokanVersion of RecordPublishe

Integrated liquid crystal optical switch based on total internal reflection

Demokan, M. S.Version of RecordPublishe

An empirical model to determine the grain size of metal-induced lateral crystallized film

Thin-film transistors (TFTs) have been fabricated using the nickel-seeded metal-induced lateral crystallization (MILC), in which an amorphous silicon is crystallized to form a large grain polysilicon film. Single crystal SOI, solid phase crystallization (SPC), and MILC TFTs were fabricated and the carrier mobilities extracted. Different types of devices have different variations in electrical properties. An empirical model based on the presence of the grain boundaries is proposed to explain the experimental results. The experimental data was used to extract the model parameters and the number of grains and grain size present in the device channel. The results can be further used to optimize the crystallization process and the device design

Electron-beam double resist process to enhance bright field pattern resolution

Electron-beam direct write is a promising technique for deep submicron lithography. One of the common methods to define a bright field pattern for the gate electrode masking uses negative resist. However, the resolution of many popular negative resists is low compared to that of positive resists. A technique is demonstrated that takes advantage of positive resist, such as polymethylmethacrylate and converts it to a bright field masking step. The technique involves (1) using a negative resist coating on a positive resist pattern, (2) plasma etching the negative resist down to the top of the positive resist, (3) exposing large area with electrons or deep ultraviolet photons, and (4) developing the result with a ratio of methyl isobutyl ketone and isopropanol. The resulting bright field masking provides high-resolution dense line patterns, which are difficult to achieve using the common negative resists alone. (C) 2002 American Vacuum Society

Fabrication of gate-all-around transistors using metal induced lateral crystallization

Gate-all-around transistor (GAT) is demonstrated. The device can be fabricated on either a bulk silicon wafer or on the top of any device layers. The fabrication process used a new technique called metal-induced-lateral-crystallization (MILC) to recrystallize the amorphous silicon to form large silicon grain in the active area. Using this technique, the transistor performance is comparable to a SOI MOSFET. Compared with the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) device, MILC GAT has lower subthreshold slope, lon er threshold voltage, higher transconductance and nearly double drive current. The impact of short channel length was investigated

Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization

A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology The first layer of transistors was formed on the SOI. The second layer of transistors was built on large-grain polysilicon-on-insulator (LPSOI), The recrystallized film was formed by the recrystallization of amorphous silicon using metal-induced lateral crystallization (MILC). The devices from the lower and upper layers were characterized and the result indicated that the SOI and LPSOI devices have similar electrical characteristics. The 3-D circuit design and layout considerations will be introduced. The 3-D CMOS inverters were demonstrated with p-channel devices stacking over the n-channel ones. The ring-oscillator showed that the 3-D circuit has 30\% reduction in the layout area and it operated at power supply as low as 0.5 V, The lower propagation delay and load capacitance suggest that 3-D circuit has higher performance than the conventional two-dimensional (2-D) circuit

Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis

In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187\%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17\% of gate length

The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistors

High-performance low-voltage thin-film transistors (TFTs) can be fabricated by grain-enbancement methods such as nickel-seeded metal-induced lateral crystallization (MILC). Electrical characteristics of the TFTs may vary due to the existence of the grain boundaries in the device active region. To obtain the best device characteristics, the effect of grain boundaries on the device must be investigated. In this paper, the cumulative distributions of the device properties such as leakage current, threshold voltage, subthreshold slope, and field-effect mobility as a function of different channel lengths and widths were studied. In general, the grain boundary effects decrease with device size. Devices with short channel lengths and wide channel widths may suffer from degradation due to large leakage current. Moreover, the effects due to the location of the nickel-seeding region on device characteristics were investigated. These include the effect of the longitudinal and lateral grain boundaries and the distance between the nickel seeding region and the device. Finally, a design guideline to reduce the grain boundary effect is presented

3D integrated circuit using large grain polysilicon film

3-D CMOS IC Technology built on two layers of large grain polysilicon is presented. These stacked layers are vertically interconnected allowing shorter interconnect to improve the logic speed. The large grain polysilicon-on-insulator (LPSOI) film is formed by the recrystallization of amorphous silicon through Metal Induced Lateral Crystallization (MILC). The crystallization region obtained can cover multiple transistors and the grain size is much larger than the transistor size. An oxide layer separates two layers of devices and forms an interlayer dielectric. The electrical performance of the LPSOI devices is presented. Inverters. ring-oscillators and shift registers further confirm that the recrystallized techniques forming the 3-D structures are feasible

Parkinsonian signs are associated with subtle functional deterioration in community-dwelling Chinese older persons

Objective: To report the prevalence of mild parkinsonian signs and their association with functional impairment in a population-based study of clinically non-demented Chinese persons. Participants and Methods: A random sample of 765 Chinese older persons from a thematic household survey was recruited. There were 389 normal elderly controls (Clinical Dementia Rating = 0), 291 with mild cognitive impairment, and 85 with very mild dementia. The prevalence of mild parkinsonian signs and its association with everyday functional performance were investigated. Results: Mild parkinsonian signs were defined as a score of 2 or more in the Unified Parkinson's Disease Rating Scale-motor section. The prevalence of mild parkinsonian signs was 16.5%, 33.0% and 49.4% in the normal controls, those with mild cognitive impairment and very mild dementia, respectively. In each group, subjects with mild parkinsonian signs had lower functional scores than those without such signs, even after adjusting for the effect of age, sex, and education. Abnormality in axial function, bradykinesia, and rigidity were associated with lower scores for Instrumental Activities of Daily Living, and rigidity was associated with lower Basic Activities of Daily Living scores. Conclusion: The prevalence of mild parkinsonian signs increased with the severity of cognitive impairment in clinically non-demented older persons. Such signs were associated with functional impairment in older persons with mild cognitive impairment and very mild dementia. © 2008 Hong Kong College of Psychiatrists.link_to_subscribed_fulltex