Impact of GC Design on Power and Performance for Android

Small mobile devices have evolved to versatile computing systems. Android devices run a complete software stack, including a full Linux kernel, user land with several software daemons and a virtual machine to run applications. On these mobile systems energy is a scarce resource and needs to be handled carefully. Current systems rely on governors that adjust the frequency of individual cores depending on the system load. We measure energy consumption of different components of this complex software stack, including garbage collection (GC) of the Android virtual machine. Here we propose several extensions to the default GC configuration of Android, including a generational collector, across established dimensions of heap memory size and concurrency. Our evaluation shows that Android's asynchronous GC thread consumes a significant amount of energy. Therefore, varying the GC strategy can reduce total on-chip energy (by 20--30%) whilst slightly impacting application throughput (by 10--40%) and increasing worst-case pause times (by 20--30%). Our work quantifies the direct impact of GC on mobile system, enumerates the main factors and layers of this relationship, and offers a guide for analysis of memory behavior in understanding and tuning system performanc

Transaction Level Error Susceptibility Model for Bus Based SoC Architectures

System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls for focus on reliability issues in such bus based systems. In this paper, we provide a detailed analysis of different kinds of errors and the susceptibility of such systems to such errors on various components that the bus comprises of. With elaborate experiments we determine the effect of a single bit error on the bus system during the course of different transactions. The work demonstrates the fact that only a few signals in a bus system are really critical and need to be guarded. Such transaction based analysis helps us to develop an effective prediction methodology to predict the effect of a single bit error on any application running on a bus based architecture. We demonstrate that our transaction based prediction scheme works with an average accuracy of 92% over all the benchmarks when compared with the actual simulation results