Faster-than-at-speed execution of functional programs: an experimental analysis

International audienceBurn-In (BI) test is usually applied in manufacturing process to screen out chip early life failures, especially for safety critical applications. Unfortunately, this test method has elevated costs for companies. In recent days, Faster-than-at-Speed-Test (FAST) has become a useful technique to discover small delay defects. At the same time, overclocking methods to enhance system performances have been studied, which focus on temperature management to preserve system functionalities. In this paper, a FAST technique is approached with the aim of intentionally provoking a thermal overheating in the microprocessor by mean of the execution of functional test programs, partly regardless of system behavior preservation. The goal is to introduce an internal stress stronger than current procedures used during BI in order to speed up early detection of latent faults. The method illustrates how to avoid blocking configurations due to timing constraints violation and leads to a significant increase of the switching activity. Experimental results on a MIPS architecture show that, by using the described technique, the processor is not falling into an unpredictable state even at frequencies up to about 20 times higher than the nominal one and the switching activity is increasing up to 300% per nanoseconds

Improving stress quality for SoC using faster-than-at-speed execution of functional programs

International audienceAt the end of the manufacturing cycle of digital circuits, a stress phase is mandatory in order to remove from the final device population the weak devices that may result in early life failures. Devices used in safety critical environments must undergo this phase that is usually accomplished by exploiting the Burn-In (BI) process. Unfortunately, BI has elevated costs for companies and current state of the art techniques are trying to reduce its cost.In recent days, Faster-than-at-Speed-Test (FAST) has become a useful technique to discover small delay defects. At the same time, overclocking methods to enhance system performances have been studied, which focus on temperature management to preserve system functionalities. In this contribution, a FAST technique is proposed with the aim of intentionally provoking a thermal overheating in the microprocessor by mean of the execution of FAST functional test programs; in other words, functional procedures are executed at higher than nominal frequencies. The goal is to introduce an internal stress stronger than current procedures used during BI in order to speed up early detection of latent faults.Being the functional stress procedures executed at faster than nominal speed, the original behaviour may not be preserved and therefore non-functional states may be reached. In this contribution, it is illustrated how to avoid blocking configurations due to timing constraints violation and how to obtain a significant increase of the switching activity by carefully increasing the clock frequency. Furthermore, a novel strategy is proposed to generate a suitable set of Faster-than-At-Speed stress programs capable to thoroughly stress processor cores.Experimental results carried out on a MIPS-like architecture show major achievements of the methodology: the processor may work at frequencies up to about 20 times higher than the nominal one without falling into an unpredictable state and the switching activity is increasing up to 300% per ns

Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLASH erase time uncertainties; at the Automatic Test Equipment (ATE) level, the strategy relies on power monitors and tester intelligence. The paper reports experimental results on a SoC manufactured by STMicroelectronics; figures show an optimized usage of stress resources and demonstrates a reduction of 25% of the BI test time when using the proposed adaptive techniques

A DMA and CACHE-based stress schema for burn-in of automotive microcontroller

Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also some experimental results gathered in an automotive microcontroller, and a comparison between traditional and parallelized burn-in stress technique is also provided

An Optimized Test During Burn-In for Automotive SoC

The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoCs). This paper proposes an optimized Test-During-Burn-In (TDBI) flow that takes advantage of the parallel execution of several types of stress procedures in which many components are carefully interleaved. The proposed methodology permits to significantly reduce the BI time and enables production monitoring by providing detailed test data-logging capabilities helping the debug of potential yield issues largely caused by the ageing of Burn-In tester consumable parts. The paper describes an experimental scenario about TDBI of an automotive SoC manufactured by STMicroelectronics

An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In

Safety-critical electronics components require thermal and electrical stress phases at the end of manufacturing test to screen weak devices. It is possible to optimize the stress induced during the screening phase of Burn-In by running in parallel different types of stress procedures. In previous works, stress procedures of CPU, RAM memory and FLASH memory have been interleaved using DMA and leveraging on instruction CACHE memory. This paper presents a novel approach for optimizing stress procedures at CPU level using an Evolutionary Algorithm. The evolutionary-based framework improves the stress of the CPU procedure when it runs in presence of a parallel stress schema. The manuscript also reports the results gathered by exploiting the evolutionary strategy in a device used in common automotive systems