CMOS-compatible dense arrays of Ge quantum dots on the Si(001) surface: hut cluster nucleation, atomic structure and array life cycle during UHV MBE growth

We report a direct observation of Ge hut nucleation on Si(001) during UHV molecular beam epitaxy at 360°C. Nuclei of pyramids and wedges were observed on the wetting layer (WL) (M × N) patches starting from the coverage of 5.1 Å and found to have different structures. Atomic models of nuclei of both hut species have been built as well as models of the growing clusters. The growth of huts of each species has been demonstrated to follow generic scenarios. The formation of the second atomic layer of a wedge results in rearrangement of its first layer. Its ridge structure does not repeat the nucleus. A pyramid grows without phase transitions. A structure of its vertex copies the nucleus. Transitions between hut species turned out to be impossible. The wedges contain point defects in the upper corners of the triangular faces and have preferential growth directions along the ridges. The derived structure of the {105} facet follows the paired dimer model. Further growth of hut arrays results in domination of wedges, and the density of pyramids exponentially drops. The second generation of huts arises at coverages >10 Å; new huts occupy the whole WL at coverages ~14 Å. Nanocrystalline Ge 2D layer begins forming at coverages >14 Å

Ge quantum dot arrays grown by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface: nucleation, morphology and CMOS compatibility

Issues of morphology, nucleation and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (<600 deg C) and high (>600 deg. C) temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts---pyramids and wedges---are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001) surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001) quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.Comment: 30 pages, 11 figure