10 research outputs found
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs
Full text linkReducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms
No full textA framework for concurrency control in real-time distributed collaboration for mobile systems
No full textA stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
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PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test
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