Enabling Supervised and Unsupervised Learning for EDA and Cybersecurity in VLSI Systems

The continuous advances in computer architectures and transistor technologies have led to exceptionally high design complexity of modern IC design solutions. Simultaneously, design objectives have evolved over years – speed and area in 1970’s-1980’s were extended to encompass noise and power in 1990’s-2000’s and further extended to hardware security in modern ICs. To deal with exponentially increasing search space of hardware design and security problems, numerous algorithms for (semi) automatic IC design have evolved as an untraceable pile of heuristics, trading off solution optimality for reasonable execution time. With an all-time high design complexity, traditional heuristics yield prohibitively suboptimal solutions, provide no convergence guarantees, and are no longer cost-effective. Thus, new computational approaches to these problems are required. Machine learning (ML) artificial intelligent methods (AI) can significantly improve the traditional EDA. While there is a general agreement on the potential benefits of AI assisted EDA, how to intelligently map the individual EDA problems and objectives into the AI domain remains an open question. Physically connecting numerous placed devices while avoiding regions occupied by other devices is a fundamental EDA problem known as multiterminal obstacle-avoiding pathfinding and is NP-hard. To mitigate the design time complexity, traditional multiterminal obstacle avoiding pathfinding algorithms exploit approximation heuristics As a result, the quality of the pathfinding solution degrades with problem complexity (due to suboptimality of the underlying decomposition approximations), and runtime lacks the benefits of paralellisation on branchless hardware (due to graph-traversing nature of the underlying point-to-point pathfinding methods). In contrast, we propose to redefine pathfinding as a typical image translation (the problem of generating a synthetic version of an image with a desired modification) and solve the new problem with deep learning. As part of the developed framework, DNN is trained to interpret a pathfinding task as a graphical bitmap and consequently generate a pathfinding solution within another bitmap using image processing methods. Another pressing concern in highly complex modern ICs is the surge in cybersecurity threats and the corresponding increase of cyber search space. the possibility of HT detection with traditional logic testing or physical inspection methods is almost nonexistent in modern many billion transistor ICs. To demonstrate the new approach, a cybersecurity framework is developed, comprising analytical expressions, AI algorithms, and statistical analysis methods. We establish and demonstrate important proximity relations between HT payload and triggering IC nodes using this theoretical groundwork. In this thesis, we investigate the complex relations among voltage variations at numerous on-chip nodes, including the node at which an attack is executed. The approach is based on statistical runtime analysis of power profiles sensed with individual on-chip sensors. The proposed design framework comprises a set of ML methods for power profile analysis, algorithms for determining sensor coverage and preferred sensor placement, and circuits for efficiently detecting and mitigating PAAs. A broad spectrum of supervised and unsupervised AI methods is investigated and a solutions for addressing the critical problem of VLSI training data is proposed. The objective of the proposed AI architectures, models, algorithms, and methodologies is to shift EDA paradigms toward fundamentally novel ML assisted solutions. Based on the demonstrated results, such ML assisted solutions can be utilized to (i) provide a means for mitigating runtime complexity of various physical design steps, and (ii) enable offline and real-time detection of hardware security threats