A 2D quantum dot array in planar ²⁸Si/SiGe

Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 × 2 quantum dot array in a 28Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore, we characterize and control the tunnel coupling between all pairs of dots by measuring polarization lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about 30 μ eV up to approximately 400 μ eV . These experiments provide insightful information on how to design 2D quantum dot arrays and constitute a first step toward the operation of spin qubits in 28Si/SiGe quantum dots in two dimensions.QCD/Vandersypen LabQCD/Veldhorst LabBUS/TNO STAFFQCD/Scappucci LabQN/Veldhorst LabQN/Vandersypen La

On-chip integration of Si/SiGe-based quantum dots and switched-capacitor circuits

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors, and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.QCD/Vandersypen LabQuTechBusiness DevelopmentQCD/Veldhorst LabQCD/Scappucci LabQID/Ishihara Lab(OLD)Quantum Integration TechnologyQN/Vandersypen La