710 research outputs found

    On the time-dependent transport mechanism between surface traps and the 2DEG in AlGaN/GaN devices

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    The physical mechanisms involved in the trapping and de-trapping processes associated to surface donor traps in GaN transistors are discussed in this work. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a Metal-on-Insulator Field-Effect-Transistor (MISFET) and explain the influence of the electric field and energy barrier on the transient time associated to the trapping and de-trapping mechanisms of surface traps. The comparison between three test-structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test-structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors

    On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

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    The robustness of ultra-high voltage (>10kV) SiC IGBTs comprising of an optimized retrograde p-well is investigated. Under extensive TCAD simulations, we show that in addition to offering a robust control on threshold voltage and eliminating punch-through, the retrograde is highly effective in terms of reducing the stress on the gate oxide of ultra-high voltage SiC IGBTs. We show that a 10 kV SiC IGBT comprising of the retrograde p-well exhibits a much-reduced peak electric field in the gate oxide when compared with the counterpart comprising of a conventional p-well. Using an optimized retrograde p-well with depth as shallow as 1 Ī¼m, the peak electric field in the gate oxide of a 10kV rated SiC IGBT can be reduced to below 2 MV.cm -1 , a prerequisite to achieve a high-degree of reliability in high-voltage power devices. We therefore propose that the retrograde p-well is highly promising for the development of>10kV SiC IGBTs

    Investigation of the Dual Implant Reverse-Conducting SuperJunction Insulated-Gate Bipolar Transistor

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    This letter presents the Dual Implant SuperJunction (SJ) trench Reverse-Conducting (RC) Insulated Gate Bipolar Transistor (IGBT) concept with two implanted SJ pillars in the drift region; one from the cathode side and another from the anode side. The proposed device is compatible with current manufacturing processes and enables a full SJ structure to be achieved in a 1.2kV device as alignment between the pillars is not required. Extensive Technology Computer Aided Design (TCAD) simulations have been performed and demonstrated that utilising this dual implantation technique can result in a 77% reduction in turn-off losses for a full SJ structure, compared to a conventional RC-IGBT. The results show that any snapback in the on-state waveform significantly increases the turn-off losses and only a deep SJ device (pillar gap < 10Ī¼m) warrants the additional processing expense
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