Compiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems

In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme. Scratch-pad allocation methods primarily are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the software-maintained cache tags. Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees, just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior. We propose a dynamic allocation methodology for global and stack data and program code that (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100% predictable memory access times. In this method data that is about to be accessed frequently is copied into the scratch-pad using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary. When compared to an existing static allocation scheme, results show that our scheme reduces runtime by up to 39.8% and energy by up to 31.3% on average for our benchmarks, depending on the SRAM size used. The actual gain depends on the SRAM size, but our results show that close to the maximum benefit in run-time and energy is achieved for a substantial range of small SRAM sizes commonly found in embedded systems. Our comparison with a direct mapped cache shows that our method performs roughly as well as a cached architecture in runtime and energy while delivering better real-time benefits

ABSTRACT Compiler-Decided Dynamic Memory Allocation for Scratch-Pad Based Embedded Systems

This paper presents a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme [4]. Existing scratch-pad allocation methods are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the software-maintained cache tags. Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. For example, our previou

Can We Predict Early Endoscopic Third Ventriculostomy Failure? The Role of Ultra-Early Postoperative Magnetic Resonance Imaging in Predicting Early Endoscopic Third Ventriculostomy Failure

Background: The success of endoscopic third ventriculostomy (ETV) depends on multiple preoperative and intraoperative factors. The multifactorial influence adds an element of unpredictability to the outcome of the most well-planned procedure. Clinical symptoms and signs may not reflect the status of the ETV stoma postprocedure and the morbidity associated with ETV failure could be catastrophic. In this study, the authors look at the role of early magnetic resonance imaging (MRI) to predict failure to avoid morbidity secondary to malfunction and propose a modified success criterion to guide treatment plan post-ETV failure. Our aim is to prospectively and retrospectively study the use of early postoperative MRI in predicting potential early ETV failure. Methods: Patients who underwent ETV at Amrita Institute of Medical Sciences from March 2011 to August 2017. The study was a retrospective and prospective observational blinded study. Inclusion criteria included patients with any form of obstructive hydrocephalus who underwent ETV and had undergone an early postoperative MRI in the first 48 hours—or latest by discharge—with a follow-up of at least 3 months. The patient details and the presence of the flow void in the immediate postoperative MRI were documented. Follow-up was for at least 3 months to identify early failures. Results: A total of 67 ETVs were performed in 65 patients. At 3 months follow-up, of the 59 ETVs with flow void on MRI, 53 were successful, whereas 6 failed. Of the 8 without flow void, 4 were successful. The overall sensitivity was 93.0, whereas specificity was 40.0. With increasing age, the negative predictive value improved from 25% in age 5 years, with an accuracy reaching 96% to predict failure of ETV. Conclusions: An early postoperative MRI is very sensitive to failure of ETV, but not highly specific. The negative predictive value and accuracy of MRI improve significantly with increasing age and in non-hemorrhagic non-infective obstructive etiology. Key words: Complications, Endoscopic third ventriculostomy, Flow voi

Dynamic Allocation for Scratch-Pad Memory using Compile-Time Decisions

In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme. Scratch-pad allocation primarily methods are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the softwaremaintained cache tags. Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior. It is easy to see why a data allocation that never changes at runtime cannot achieve the full locality benefits of a cache. We propose a dynamic allocation methodology for global and stack data and program code that, (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100 % predictable memory access times. In this method dat

Heap Data Allocation to Scratch-Pad Memory in Embedded Systems

Abstract — This paper presents the first-ever compiletime method for allocating a portion of the heap data to scratch-pad memory. A scratch-pad is a fast directly addressed compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in access time, energy consumption, area and overall runtime. Existing compiler methods for allocating data to scratch-pad are able to place only global and stack data in scratch-pad memory; heap data is allocated entirely in DRAM, resulting in poor performance. Runtime methods based on software caching can place heap data in scratchpad, but because of their high overheads from software address translation, they have not been successful, especially for heap data. In this paper we present a dynamic yet compiler-directed allocation method for heap data that for the first time, (i) is able to place a portion of the heap data in scratch-pad; (ii) has no software-caching tags; (iii) requires no run-time per-access extra address translation; and (iv) is able to move heap data back and forth between scratch-pad and DRAM to better track the program’s locality characteristics. With our method, global, stack and heap variables can share the same scratch-pad. When compared to placing all heap variables in DRAM and only global and stack data in scratch-pad, our results show that our method reduces the average runtime of our benchmarks by 34.6%, and the average power consumption by 39.9%, for the same size of scratch-pad fixed at 5 % of total data size. Index Terms — heap allocation, scratch pad, SRAM, tightly coupled memory, TCM, dynamic allocation. I