Design Time Optimization for Hardware Watermarking Protection of HDL Designs

HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time

Fast Implementation Of Orthogonal Wavelet Filterbanks Using Field-Programmable Logic

Field-Programmable Logic (FPL) is on the verge of revolutionizing digital signal processing (DSP) in the manner that programmable DSP microprocessors did nearly two decades ago. While FPL densities and performance have steadily improved to the point where some DSP solutions can be integrated into a single FPL chip, they still have limited the use in high-precision high-bandwidth applications. In this paper it is shown that alternative implementation strategies can be found which overcome the precision/bandwidth barrier. The design of Daubechies length 4 and 8 filter is presented to compare FPL and programmable DSP solutions. 1. INTRODUCTION FPLs appear in two forms, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). FPGAs are fine grain devices consisting of small logic elements (LE) (e.g., Xilinx XC4000) and various different routing canals (short, local, and long-lines). CPLDs have larger logic blocks and fast busses connecting these array blocks ..

Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs

Distributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures