A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled

An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity Ü

Abstract — An all-MOS linear voltage-to-frequency converter (VFC) chip with 520 KHz/V sensitivity is presented in this paper. This circuit converts an input voltage into frequency by charging and discharging a capacitor. An all-MOS voltage window comparator (VWC) with reduced propagation delay is designed to improve the linearity of traditional VFCs. The propagation delay of the VWC is discussed to resolve the tradeoff between bandwidth and linearity of VFC. The proposed VFC is verified on silicon using TSMC (Taiwan Semiconductor Manufacturing Company) 1P5M 0.25�m process. The measurement results show that the linearity error is less than 1%, and the sensitivity is 520 KHz/V at the input voltage range from 0.1 to 0.8 V