On the Design of a Self-Reconfigurable SoPC Based Cryptographic Engine

Abstract — This paper presents a SoPC (System-ona-Programmable-Chip) embedded system featuring selfreconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported in this paper show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA

Practical Design of a Computation and Energy Efficient Hardware Task Scheduler in Embedded Reconfigurable Computing Systems

By utilizing massively parallel circuit design in FP-GAs, the overall system efficiency, in terms of computation efficiency and energy efficiency, can be greatly enhanced by offloading some computation-intensive tasks which are originally executed in the instruction set processor to the FPGA fabric. In essence, a hardware task scheduler is needed. However, most of the work in the literature considers scheduling algorithms which are unable or difficult to be implemented using the design flows in current development platform. Moreover, little of the work takes energy consumption into consideration. In this paper, we present the design of a hardware task scheduler which takes energy consumption into consideration, and can be readily implemented using current design flows. 1

Multi-core design and resource allocation: from big core to ultra-tiny core

published_or_final_versionElectrical and Electronic EngineeringDoctoralDoctor of Philosoph

High performance embedded reconfigurable computing: data security and media processing applications

abstractpublished_or_final_versionElectrical and Electronic EngineeringMasterMaster of Philosoph