An investigation of grain boundary phase transitions at elevated temperatures by TEM

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 1988.Includes bibliographical references.by Tsung-Eong Hsieh.Ph.D

The Fabrication of Indium–Gallium–Zinc Oxide Sputtering Targets with Various Gallium Contents and Their Applications to Top-Gate Thin-Film Transistors

We prepared amorphous indium–gallium–zinc oxide (a-IGZO) thin films with various Ga content ratios and investigated their feasibility as the active channel layers of top-gate thin-film transistors (TFT). First, the 2-inch IGZO sputtering targets with stoichiometric ratios of InGaZn2O5, InGaZnO4, and InGa2ZnO5.5 were fabricated using In2O3, Ga2O3, and ZnO oxide powders as raw materials via sintering treatments at temperatures ranging from 900 °C to 1300 °C for 6 h or 8 h. X-ray diffraction analysis indicated that the InGaZn2O5 and InGaZnO4 targets are single-phase structures whereas the InGa2ZnO5.5 target is a two-phase structure. Hall effect measurement indicated that the a-InGaZn2O5 and a-InGaZnO4 layers possess a carrier concentration (N) of about 1019 cm−3 and a resistivity (ρ) of about 10−2 Ω·cm; however, the N of the a-InGa2ZnO5.5 layer is only 1017 cm−3, and the ρ is about 1 to 4 Ω·cm. Moreover, the a-InGaZn2O5 layer exhibited the highest Hall-effect mobility (μHall) of 21.17 cm2·V−1·sec−1. This indicated that the impedance of Ga3+ ions to carrier migration is the main factor affecting the electrical properties of a-IGZO layers. Ga content in the a-IGZO channel similarly affects the performance of the TFT devices prepared in this study. The annealing at 300 °C for 1 h in an ambient atmosphere was found to significantly improve the electrical properties of the TFT devices. The best performance was observed in the a-InGaZnO4 TFT sample subjected to post-annealing at 300 °C with Vth = −0.85 V, μFE = 8.46 cm2, V−1·sec−1, SS = 2.31, V·decade−1, and Ion/Ioff = 2.9 × 104

Electrical and Hysteresis Characteristics of Top-Gate InGaZnO Thin-Film Transistors with Oxygen Plasma Treatment Prior to TEOS Oxide Gate Dielectrics

We report the impact of oxygen (O2) plasma time on an amorphous indium–gallium–zinc oxide (a-IGZO) thin-film surface that was carried out before TEOS deposition in order to optimize the performance of thin-film transistors (TFTs). TheO2 plasma time of 60 s possessed the largest on/off current ratio of >108, with a field-effect mobility (µFE) of 8.14 cm2 V−1 s−1, and the lowest subthreshold swing (S.S.) of 0.395 V/decade, with a threshold voltage (Vth) of −0.14 V. However, increases in Ioff and S.S. and decreases in the µFE were observed for the longer O2 plasma time of 120 s. As the O2 plasma time increased, the reduction in the carrier concentration in the IGZO channel layer may have resulted in an increase in Vth for the IGZO TFT devices. With an increase in the O2 plasma time, the surface roughness of the IGZO channel layer was increased, the carbon content in the TEOS oxide film was reduced, and the film stoichiometry was improved. The SIMS depth profile results showed that the O/Si ratio of TEOS oxide for the sample with the O2 plasma time of 60 s was 2.64, and its IGZO TFT device had the best electrical characteristics. In addition, in comparison to the IGZO TFT device without O2 annealing, larger clockwise hysteresis in the transfer characteristics revealed that a greater number of electrons were trapped at the interface between TEOS oxide and the a-IGZO channel layer. However, hysteresis curves of the O2-annealed IGZO TFTs with various O2 plasma times were greatly reduced, meaning that the electron traps were reduced by O2 annealing

Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier’s law of heat conduction at steady-state

Fourier’s law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ’s) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR’s) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays