A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine

As technologies continue to shrink, industry seeks even faster ultra-low power ICs, requiring more accurate estimation of the worst case delay. Although traditional Static Timing Analysis (STA) methods incorporate data regarding interconnects and noise over power supply networks, they are still considered to be overly pessimistic. The only way to accurately capture dynamic effects in the estimation of the worst case delay is through Dynamic Timing Analysis (DTA). In this paper we propose a novel methodology to precisely estimate a tight upper bound of the worst case delay, using Extreme Value Theory on the results of voltage drop-aware simulation. © 2018 IEEE

A design flow for the precise identification of the worst-case voltage drop in power grid analyses

Modern IC designs contain hundreds of millions of transistors and new implementations of multi core chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow based on innovative results from recent research work. This approach demonstrates a new implementation of construction of the current space which is performed via plain simulation and statistical extrapolation using results from extreme value theory. Experimental results verify the potential of the estimation engine within an industrial EDA flow for performing power grid verification using a custom hierarchical design. © 2008 IEEE

An RTL-to-grid design flow for power grid verification based on a statistical estimation engine

The most important reliability problem of modern power distribution networks is the voltage drop or IR-drop problem. In this paper we present a design flow based on industrial tools for power grid verification, where the grid is modeled as a linear resistive network and the necessary maximum current estimates are statistically obtained by recent advances in the field of extreme value theory. Experimental results include the verification of power grid for a choice of different real designs. © 2006 IEEE

Fast Transform-based preconditioners for large-scale power grid analysis on massively parallel architectures

Efficient analysis of massive on-chip power delivery networks is among the most challenging problems facing the EDA industry today. In this paper, we present a new preconditioned iterative method for fast DC and transient simulation of large-scale power grids found in contemporary nanometer-scale ICs. The emphasis is placed on the preconditioner which reduces the number of iterations by a factor of 5X for a 2.6M-node industrial design and by 72.6X for a 6.2M-node synthetic benchmark, compared with incomplete factorization preconditioners. Moreover, owing to the preconditioner's special structure that allows utilizing a Fast Transform solver, the preconditioning system can be solved in a near-optimal number of operations, while it is extremely amenable to parallel computation on massively parallel architectures like graphics processing units (GPUs). Experimental results demonstrate that our method achieves a speed-up of 214.3X and 138.7X for a 2.6M-node industrial design, and a speed-up of 1610.5X and 438X for a 3.1M-node synthetic design, over state-of-the-art direct and iterative solvers respectively when GPUs are utilized. At the same time, its matrix-less formulation allows for reducing the memory footprint by up to 33% compared to the memory requirements of the best available iterative solver. © 2012 ACM

A power grid analysis and verification tool based on a statistical prediction engine

Voltage drops are one of the most stringent problems in modern IC implementation, which is exacerbated by the ever decreasing transistor sizes and interconnect line widths. In order to find the true worst case voltage drop that a power net of a design might suffer, the designer would have to check the voltage drops that occur from the simulation of all possible input vector pairs of a design. This is a prohibitive amount of simulations for modem ICs that have hundreds of inputs. Consequently, designers face two basic challenges, fast and accurate estimation of worst case voltage-drop and accurate modeling of the power distribution network. In this paper we present a voltage-drop aware tool for power grid analysis and verification based on a statistical engine, which can estimate the true worst case voltage drops on a design with a typical confidence level of 99%. The statistical engine is based on extensions to the Extreme Value Theory (EVT) which is a pertinent field of statistics for the estimation of the unknown maximum of a related population from one (or more) of its samples. The paper shows how the statistical engine can take input from gate-level simulation of digital logic, combined with transient simulation of the power and ground network with inductance-aware (RLCK) models. Using these techniques, a designer can estimate the true worst case voltage drop on each and every contact of the power and ground distribution network of a digital design, using a relatively small amount of input vectors, thus greatly reducing the turnaround time for power integrity verification. ©2010 IEEE