A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number

[EN] The computation of the arctangent of a complex number, i.e., the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In this brief, we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a first stage that performs a coarse approximation of the atan2 function and a second stage that improves the output accuracy by means of a lookup table. We present results for fixed-point implementations in a field-programmable gate array device, all of them guaranteeing last-bit accuracy, which provide an advantage in latency, speed, and use of resources, when compared with well-established fixed-point options.This work was supported by the Spanish Ministerio de Economia y Competitividad and FEDER under Grant TEC2015-70858-C2-2-R.Torres Carot, V.; Valls Coquillat, J. (2017). A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25(9):2663-2667. https://doi.org/10.1109/TVLSI.2017.2700519S2663266725

Fast- and Low-Complexity atan2(a,b) Approximation

[EN] This article presents a new entry to the class of published algorithms for the fast computation of the arctangent of a complex number. Our method uses a look-up table (LUT) to reduce computational errors. We also show how to convert a large-sized LUT addressed by two variables to an equivalent-performance smaller-sized LUT addressed by only one variable. In addition, we demonstrate how and why the use of follow-on LUTs applied to other simple arctan algorithms produce unexpected and interesting results.This work is funded by the Spanish Ministerio de Economía y Competitividad and FEDER under grant TEC2015-70858-C2-2-R.Torres Carot, V.; Valls Coquillat, J.; Lyons, R. (2017). Fast- and Low-Complexity atan2(a,b) Approximation. IEEE Signal Processing Magazine. 34(6):164-169. https://doi.org/10.1109/MSP.2017.2730898S16416934

The energy balance hypothesis of obesity: do the laws of thermodynamics explain excessive adiposity?

[EN] In this work, we reflect upon the energy balance hypothesis of obesity. International organizations, the general population and many scientists hold the belief that obesity is indisputably caused by an imbalance between energy intake and energy expenditure. Most of them argue that the laws of thermodynamics support this view. We identify and review the main arguments used to support this belief, and we explain the reasoning mistakes those arguments harbor. We show that the laws of thermodynamics do not support the idea that obesity is an energy problem nor an energy balance problem more than they do in the growth of any other tissue in the human body. We argue that the validity of the energy balance paradigm for obesity must be questioned. Although correction of a wrong belief is laudable per se, in this particular case harm may arise by influencing the way in which obesity prevention is tackled and obese patients are treated.Torres Carot, V.; Suárez-González, A.; Lobato-Foulques, C. (2022). The energy balance hypothesis of obesity: do the laws of thermodynamics explain excessive adiposity?. European Journal of Clinical Nutrition. 76(10):1374-1379. https://doi.org/10.1038/s41430-021-01064-413741379761

Optimised CORDIC-based atan2 computation for FPGA implementations

This paper is a postprint of a paper submitted to and accepted for publication in Electronics Letters and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library[EN] A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture.This work was funded by the Spanish Ministerio de Economia y Competitividad and FEDER under the grant TEC2015-70858-C2-2-R.Torres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ. (2017). Optimised CORDIC-based atan2 computation for FPGA implementations. Electronics Letters. 53(19):1296-1298. https://doi.org/10.1049/el.2017.2090S12961298531

Hardware Architecture of a QAM Receiver for Short-Range Optical Communications

[EN] Short-reach optical fiber communications systems aim to achieve high throughput, in the order of tens of Gbps. The implementation of these high-speed systems requires parallel processing, which makes low-complexity designs of their subsystems a key to the successful large-scale deployment of this technology. Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was originally suggested for these systems with the goal of using as much bandwidth as possible and, therefore, achieving high communication rates. Recently, Oversampled Subcarrier Modulation (OVS-SCM) was proposed as an alternative more computational efficient than HC-SCM and also with a better spectral efficiency. This paper proposes a hardware-efficient architecture for an OVS-SCM receiver, which takes into account the inherent parallel processing of these systems. This receiver takes 16 samples in parallel from a 5 GSa/s analog-to-digital converter with a 3.2 GHz 3 dB bandwidth. Design solutions for the frame detection block, the mixer, the resampler, the fractional interpolator, the matched filter and the timing estimator are presented. Our results show that, compared to the HC-SCM receiver, this proposal reduces the computational load of the downconverter stages by 90%. FPGA implementation results are given to demonstrate that our proposal can be implemented in state-of-the-art devices.This work was supported in part by MCIN/AEI/10.13039/501100011033 under Grants RTI2018-101658-B100 and PID2021-126514OB-I00, and in part by the European Union through "ERDF Away of making Europe."Valls Coquillat, J.; Torres Carot, V.; Pérez Pascual, MA.; Almenar Terre, V. (2023). Hardware Architecture of a QAM Receiver for Short-Range Optical Communications. Journal of Lightwave Technology. 41(2):451-461. https://doi.org/10.1109/JLT.2022.321735745146141

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.This research was funded by the Spanish Ministerio de Economia y Competitividad and FEDER grant number TEC2015-70858-C2-2-RTorres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ.; García Herrero, FM. (2019). Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. Electronics. 8(1):1-13. https://doi.org/10.3390/electronics8010010S11381Cideciyan, R., Gustlin, M., Li, M., Wang, J., & Wang, Z. (2013). Next generation backplane and copper cable challenges. IEEE Communications Magazine, 51(12), 130-136. doi:10.1109/mcom.2013.6685768Koetter, R., & Vardy, A. (2003). Algebraic soft-decision decoding of reed-solomon codes. IEEE Transactions on Information Theory, 49(11), 2809-2825. doi:10.1109/tit.2003.819332Sudan, M. (1997). Decoding of Reed Solomon Codes beyond the Error-Correction Bound. Journal of Complexity, 13(1), 180-193. doi:10.1006/jcom.1997.0439Guruswami, V., & Sudan, M. (1999). Improved decoding of Reed-Solomon and algebraic-geometry codes. IEEE Transactions on Information Theory, 45(6), 1757-1767. doi:10.1109/18.782097Jiang, J., & Narayanan, K. R. (2008). Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information. IEEE Transactions on Information Theory, 54(9), 3907-3928. doi:10.1109/tit.2008.928238Jiangli Zhu, Xinmiao Zhang, & Zhongfeng Wang. (2009). Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11), 1602-1615. doi:10.1109/tvlsi.2008.2005575Jiangli Zhu, & Xinmiao Zhang. (2008). Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10), 3050-3062. doi:10.1109/tcsi.2008.923169Zhongfeng Wang, & Jun Ma. (2006). High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(9), 937-950. doi:10.1109/tvlsi.2006.884046Zhang, X. (2006). Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1156-1161. doi:10.1109/tvlsi.2006.884177Xinmiao Zhang, & Parhi, K. K. (2005). Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(4), 413-426. doi:10.1109/tvlsi.2004.842914Bellorado, J., & Kavcic, A. (2010). Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part I: An Algebraic Soft-In Hard-Out Chase Decoder. IEEE Transactions on Information Theory, 56(3), 945-959. doi:10.1109/tit.2009.2039073García-Herrero, F., Valls, J., & Meher, P. K. (2011). High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits, Systems, and Signal Processing, 30(6), 1643-1669. doi:10.1007/s00034-011-9327-4Zhang, W., Wang, H., & Pan, B. (2013). Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 974-978. doi:10.1109/tvlsi.2012.2197030Peng, X., Zhang, W., Ji, W., Liang, Z., & Liu, Y. (2015). Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes. IEEE Communications Letters, 19(11), 1865-1868. doi:10.1109/lcomm.2015.2477495Lin, Y.-M., Hsu, C.-H., Chang, H.-C., & Lee, C.-Y. (2014). A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 2110-2118. doi:10.1109/tcsi.2014.2298282Wu, Y. (2015). New Scalable Decoder Architectures for Reed–Solomon Codes. IEEE Transactions on Communications, 63(8), 2741-2761. doi:10.1109/tcomm.2015.2445759Garcia-Herrero, F., Canet, M. J., Valls, J., & Meher, P. K. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 568-573. doi:10.1109/tvlsi.2010.210396

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding

© 2019 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] This paper presents a low-complexity chase (LCC) decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide an evidence that the proposed method is suitable for RS codes with different rates and Galois fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at the frame error rate that is equal to 10(-6) compared with hard-decision decoding, which is higher than that of an eta = 5 LCC. The implementation results in ASIC show that a throughput of 3.6 Gb/s can be reached in a 90-nm process and 29.1XORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gb/s and requires 5085 LUTs.This work was supported by the Spanish Ministerio de Economia y Competitividad and FEDER under Grant TEC2015-70858-C2-2-R. This paper was recommended by Associate Editor M. Boukadoum.Valls Coquillat, J.; Torres Carot, V.; Canet Subiela, MJ.; García-Herrero, FM. (2019). A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Transactions on Circuits and Systems I Regular Papers. 66(6):2198-2207. https://doi.org/10.1109/TCSI.2018.2882876S2198220766

Hardware architecture of a gaussian noise generator based on inversion method

In this brief, we present a hardware-based Gaussian noise generator (GNG) with low hardware cost, high generation rate, and high Gaussian tail accuracy. The proposed generator is based on a piecewise polynomial approximation of the inverse cumulative distribution function (ICDF). We propose to avoid the area-demanding barrel-shifter of the ICDF approximation by means of creating a new uniform random sequence from the uniform random number generator output. The GNG architecture has been implemented in field-programmable gate array devices, and the implementation results are compared with other published designs, achieving a higher deviation with fewer hardware resources. Our GNG generates 242 Msps of random noise and achieves a tail of 13.1 sigma with 442 slices, two multipliers, and two Block-RAM of a Virtex-II device. The generator output successfully passed commonly used statistical tests. © 2012 IEEE.This work was supported by Fondo Europeo de Desarrollo Regional and the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2008-06787 and Grant TEC2011-27916. This brief was recommended by Associate Editor Y. Ha.Gutiérrez, RG.; Torres Carot, V.; Valls Coquillat, J. (2012). Hardware architecture of a gaussian noise generator based on inversion method. IEEE Transactions on Circuits and Systems II: Express Briefs. 59(8):501-505. doi:10.1109/TCSII.2012.2204119S50150559

Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor

This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER = 10(-15) is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm(2)This work was supported by the Spanish Ministerio de Economia y Competitividad under Grants TEC2011-27916 and TEC2012-38558-C02-02. This paper was recommended by Associate Editor J. Ma.Angarita, F.; Valls Coquillat, J.; Almenar Terre, V.; Torres Carot, V. (2014). Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor. IEEE Transactions on Circuits and Systems I: Regular Papers. 61(7):2150-2158. doi:10.1109/TCSI.2014.2304660S2150215861