Controller synthesis for application specific digital signal processors

A controller synthesizer, that is part of a design system by which algorithms unsuitable for standard processors can be implemented, is presented. A hierarchical controller architecture suitable for frame-based and multi-sample-rate algorithms is synthesized. Synthesis of a controller is based on micro instructions, specific for each architecture, and assumes no use of predefined functional blocks. The designer can affect complexity and partitioning of the controller by changing the micro program. Processors for speech scrambling and digital adjustment of quadrature modulators have been designed and fabricated

A parallel 2Gops/s image convolution processor with low I/O bandwidth

A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. Therefore, a customized processor has been designed with a tailored architecture. The processors have a total sustained calculation capacity of >2G arithmetic operations/s at 20 MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture

Implementation Issues for acoustic echo cancellers

The high computational complexity of acoustic echo cancellation algorithms requires application specific implementations to sustain real time signal processing with affordable power consumption. This is especially true for systems where a delayless approach is considered important, e.g. wireless communication systems. The proposed paper presents architectural considerations to reach a feasible hardware solution

Design and implementation of a 1024-point pipeline FFT processor

pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radi~-2 ~ algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in PLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in OSp CMOS technology and takes an area of 40 mm’. With 3.3 ~ power supply, it can compute 2n, n = 0, 1,..., 10 complex point forward and inverse FFT in real time with up to 30MHz sampling frequency. The SQNR is above 50dB for white noise input. I

A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's

This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltag

Method to Save Silicon Area by Increasing the Filter Order

The authors' intention is to show that there are other criteria when optimising digital filters than minimising the filter order. The final result in the form of minimum silicon area or few machine cycles in a high-speed custom DSP are aims that are important in a custom design process. It is not an axiom that the minimum order of the filter gives the optimum result. Algorithms with trivial coefficients will gain both in area and speed. As an example, they show a wideband digital filter for mobile communicatio

A new approach to pipeline FFT processor

A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL

A Custom Digital Intermediate Frequency Filter for the American Mobile Telephone System

A digital filter for intermediate frequency filtering in mobile communication systems is presented. The purpose of the work is to show an alternative to the analog filters which are used in most of today's heterodyne receivers. Bit-serial arithmetic is applied on a twelfth-order wave digital lattice filter algorithm. The paper also shows a method for retiming such algorithms. The power consumption in two fabricated prototypes is compared. By customizing the library cells, the power consumption has been reduced significantly. In the low power prototype, the power dissipation is 8 mW using 3 V supply voltage. The prototype is a 10 MIPS design fabricated in a 0.8-μm standard two-metal-layer CMOS proces

Controller synthesis for digital signal processors

A tool for synthesis of control units in application-specific digital signal processors is presented. Synthesis of a control unit is based on micro instructions generated for each processor module and includes no use of predefined functional blocks. Complexity and partitioning of the controller are dependent on the structure of the micro program. The control unit synthesizer has been developed for synthesis of controllers to arbitrary digital signal processor architectures. The applications are targeted at digital radio communication algorithms. A hierarchical controller architecture suitable for frame-based and multi-sample-rate algorithms is synthesized by the tool. Processors for speech scrambling and digital adjustment of quadrature modulators have been designed and fabricated