A 7–13 GHz 10 W High-Efficiency MMIC Power Amplifier in 0.25 µm GaN HEMT Process

With the increase in applications of the millimeter wave spectrum for phased array radar systems, mobile 7–13 communication systems, and satellite systems, the demand for a wideband, high-efficiency, high-power monolithic microwave integrated circuit (MMIC) power amplifier (PA) is increasing. In this paper, a 7–13 GHz 10 W high-efficiency MMIC PA is designed. This amplifier consists of a two-stage circuit structure with two high electron mobility transistor (HEMT) cells for the driver stage and four HEMT cells for the power stage. To ensure high efficiency and a certain output power (Pout), both the driver–stage and power–stage transistors use a deep Class–AB bias. At the same time, in order to further improve the efficiency, low-loss and second–harmonic tuning techniques are used in the output and inter-stage matching networks, respectively. Finally, the electromagnetic simulation results show that within a frequency of 7–13 GHz, the amplifier achieves an average saturated continuous wave (CW) Pout of 40 dBm, a small signal gain of 14.5–15.5 dB, a power-added efficiency (PAE) of 30–46%, and the input and output return loss are better than 5 dB and 8 dB, respectively

A 7–13 GHz 10 W High-Efficiency MMIC Power Amplifier in 0.25 µm GaN HEMT Process

With the increase in applications of the millimeter wave spectrum for phased array radar systems, mobile 7–13 communication systems, and satellite systems, the demand for a wideband, high-efficiency, high-power monolithic microwave integrated circuit (MMIC) power amplifier (PA) is increasing. In this paper, a 7–13 GHz 10 W high-efficiency MMIC PA is designed. This amplifier consists of a two-stage circuit structure with two high electron mobility transistor (HEMT) cells for the driver stage and four HEMT cells for the power stage. To ensure high efficiency and a certain output power (Pout), both the driver–stage and power–stage transistors use a deep Class–AB bias. At the same time, in order to further improve the efficiency, low-loss and second–harmonic tuning techniques are used in the output and inter-stage matching networks, respectively. Finally, the electromagnetic simulation results show that within a frequency of 7–13 GHz, the amplifier achieves an average saturated continuous wave (CW) Pout of 40 dBm, a small signal gain of 14.5–15.5 dB, a power-added efficiency (PAE) of 30–46%, and the input and output return loss are better than 5 dB and 8 dB, respectively

Design of 2–16 GHz Non-Uniform Distributed GaN HEMT MMIC Power Amplifier with Harmonic Suppression Network

In this paper, an ultra-wideband (UWB) power amplifier (PA) on a 0.25 μm gallium-nitride (GaN) on silicon carbide (SiC) high-electron-mobility transistor (HEMT) process, operating in Ku-band, is presented. The broadband PA design is based on the four-stage non-uniform distributed amplifier structure. In order to improve the efficiency of the PA, a harmonic suppression network is added at the output of the drain artificial transmission line. At the same time, a capacitor is connected in series at the input of the gate, which is used to compensate for the phase offset of the gate and increase the cut-off frequency of the PA. The final gate width of the first stage is 0.56 μm, and the other three-stage gate widths are all 0.32 μm. Over the frequency range of 2–16 GHz, the simulated results of this NDPA exhibit a power-added efficiency (PAE) of 16.6–27%, a saturated continuous wave (CW) output power of 35–37 dBm, a small signal gain of 9.1–11.6 dB, and output return losses of 5–15 dB

Design of 2–16 GHz Non-Uniform Distributed GaN HEMT MMIC Power Amplifier with Harmonic Suppression Network

In this paper, an ultra-wideband (UWB) power amplifier (PA) on a 0.25 μm gallium-nitride (GaN) on silicon carbide (SiC) high-electron-mobility transistor (HEMT) process, operating in Ku-band, is presented. The broadband PA design is based on the four-stage non-uniform distributed amplifier structure. In order to improve the efficiency of the PA, a harmonic suppression network is added at the output of the drain artificial transmission line. At the same time, a capacitor is connected in series at the input of the gate, which is used to compensate for the phase offset of the gate and increase the cut-off frequency of the PA. The final gate width of the first stage is 0.56 μm, and the other three-stage gate widths are all 0.32 μm. Over the frequency range of 2–16 GHz, the simulated results of this NDPA exhibit a power-added efficiency (PAE) of 16.6–27%, a saturated continuous wave (CW) output power of 35–37 dBm, a small signal gain of 9.1–11.6 dB, and output return losses of 5–15 dB